Apparatus and Method for Power MOS Transistor

• US 20140015045A1
• Filed: 07/11/2012
• Published: 01/16/2014
• Est. Priority Date: 07/11/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Su, Po-Chih, Chou, Hsueh-Liang, Ng, Chun-Wai, Liu, Ruey-Hsin
• Granted Patent: US 9,293,376 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A power MOS transistor comprises a drain contact plug formed over a first side of a substrate, a source contact plug formed over a second side of the substrate and a trench formed between the first drain/source region and the second drain/source region. The trench comprises a first gate electrode, a second gate electrode, wherein top surfaces of the first gate electrode and the second gate electrode are aligned with a bottom surface of drain region. The trench further comprises a field plate formed between the first gate electrode and the second gate electrode, wherein the field plate is electrically coupled to the source region.

Claims

1. An apparatus comprising:

a first drain/source contact plug formed over a first side of a substrate, wherein the first drain/source contact plug coupled to a first drain/source region;

a second drain/source contact plug formed over a second side of the substrate, wherein the second drain/source contact plug coupled to a second drain/source region; and

a trench formed between the first drain/source contact plug and the second drain/source contact plug, wherein the trench comprises;

a first gate electrode;

a second gate electrode, wherein;

the first gate electrode and the second gate electrode are formed in a lower portion of the trench; and

two drift regions formed along sidewalls of an upper portion of the trench and

a field plate formed between the first gate electrode and the second gate electrode, wherein the field plate is electrically coupled to the second drain/source region.

2. The apparatus of claim 1, further comprising:

a first diffusion region comprising a first n-type drain drift region; and

a second diffusion region comprising a second n-type drain drift region, wherein the first n-type drain drift region and the second n-type drain drift region are symmetrical relative to the trench.

3. The apparatus of claim 1, further comprising:

a p-type epitaxial layer formed over the substrate; and

a p+ region formed in the p-type epitaxial layer, wherein the p+ region is electrically coupled to the field plate.

4. The apparatus of claim 3, further comprising:

a second n+ region formed between a bottom surface of the trench and the p+ region.

5. The apparatus of claim 4, wherein the second n+ region is coupled to the second drain/source contact plug through the field plate, the p+ region and the substrate.

6. The apparatus of claim 1, further comprising:

a first dielectric film formed between the first gate electrode and the field plate; and

a second dielectric film formed between the second gate electrode and the field plate.

7. The apparatus of claim 6, wherein:

the first dielectric film and the second dielectric film are formed of an oxide and have a thickness in a range from about 0.1 um to about 0.5 um.

8. The apparatus of claim 1, wherein:

the first drain/source region is a drain of a trench power transistor; and

the second drain/source region is a source of the trench power transistor.

9. A device comprising:

a drain region having a first conductivity type formed over a substrate having a second conductivity type;

a source region having the first conductivity type formed over the substrate; and

a trench formed between the drain region and the source region, wherein the trench comprise;

a first gate electrode;

a field plate formed adjacent to the first gate electrode, wherein the first gate electrode and the field plate are separated by a first dielectric film, and wherein the field plate is electrically coupled to the source region; and

a second gate electrode formed adjacent to the field plate, wherein the first gate electrode and the second gate electrode are symmetrical relative to the field plate.

10. The device of claim 9, further comprising:

a first drain-drift region coupled to the drain region; and

a second drain-drift region coupled to the drain region, wherein the first drain-drift region and the second drain-drift region are symmetrical relative to the trench.

11. The device of claim 9, further comprising:

a first epitaxial layer having the second conductivity type formed over the substrate; and

a second epitaxial layer having the first conductivity type formed over the first epitaxial layer.

12. The device of claim 9, wherein:

the first conductivity type is an n-type conductivity; and

the second conductivity type is a p-type conductivity.

13. The device of claim 9, wherein:

the first conductivity type is a p-type conductivity; and

the second conductivity type is an n-type conductivity.

14. The device of claim 9, further comprising:

a drain contact plug coupled to the drain region, wherein the drain contact plug is formed over a first side of the substrate; and

a source contact plug coupled to the source region, wherein the source contact plug is formed over a second side of the substrate.

15. A method comprising:

providing a substrate with a second conductivity type;

growing a first epitaxial layer having the second conductivity type;

growing a second epitaxial layer having a first conductivity type;

forming a trench in the first epitaxial layer and the second epitaxial layer;

forming a first gate electrode in the trench;

forming a second gate electrode in the trench;

applying an ion implantation process using the first gate electrode and the second gate electrode as ion implantation masks to form a first drain-drift region and a second drain-drift region respectively;

forming a field plate in the trench, wherein the field plate is between the first gate electrode and the second gate electrode;

forming a drain region in the second epitaxial layer, wherein the drain region has the first conductivity type; and

forming a source region in the first epitaxial layer, wherein the source region has the first conductivity type, and wherein the source region is electrically coupled to the field plate.

16. The method of claim 15, further comprising:

forming the first drain-drift region along a first sidewall of the trench; and

forming the second drain-drift region along a second sidewall of the trench, wherein upper portions of the first gate electrode and the second gate electrode are aligned with bottom portions of the first drain-drift region and the second drain-drift region.

17. The method of claim 15, further comprising:

filling free space between the field plate and the first gate electrode with a first dielectric film.

18. The method of claim 17, wherein:

the first dielectric film is formed of an oxide; and

the first dielectric film is of a thickness in a range from about 0.1 um to about 0.5 um.

19. The method of claim 15, further comprising:

forming a drain contact plug coupled to the drain region, wherein the drain contact plug is formed over a first side of the substrate; and

forming a source contact plug coupled to the source region, wherein the source contact plug is formed over a second side of the substrate.

20. The method of claim 19, further comprising:

forming a p+ region in the first epitaxial layer, wherein the source region is coupled to the source contact plug through the field plate, the p+ region and the substrate.