FinFET with Trench Field Plate

• US 20140015048A1
• Filed: 07/11/2012
• Published: 01/16/2014
• Est. Priority Date: 07/11/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Su, Po-Chih, Liu, Ruey-Hsin
• Granted Patent: US 8,921,934 B2
• Time in Patent Office: Days
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.

Claims

1. An integrated circuit device, comprising:

a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type;

a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion;

a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion;

a dielectric material formed in the trench on opposing sides of the gate; and

a field plate embedded in the dielectric material on one of the opposing sides of the gate.

2. The integrated circuit device of claim 1, wherein a source is formed at least partially within the trench proximate the body portion of the pad layer.

3. The integrated circuit device of claim 1, wherein a longest dimension of the trench is orthogonal to a longest dimension of the gate.

4. The integrated circuit device of claim 1, wherein a longest dimension of the trench is orthogonal to the interface of the body portion and the drift region portion.

5. The integrated circuit device of claim 1, wherein the dielectric material formed in the trench is disposed on at least one of trench sidewalls and a trench floor.

6. The integrated circuit device of claim 1, wherein the dielectric material formed in the trench is disposed on gate sidewalls.

7. The integrated circuit device of claim 1, wherein the gate and the field plate are each formed from a polysilicon material.

8. The integrated circuit device of claim 1, wherein a depth of the trench is less than a height of the gate.

9. The integrated circuit device of claim 1, wherein top surfaces of the field plate and the dielectric material are co-planar.

10. The integrated circuit device of claim 1, wherein a floor and sidewalls of the trench adjacent the body portion are doped with the second doping type in a doping concentration higher than that of the drift region portion.

11. The integrated circuit device of claim 1, wherein the drift region portion of the pad layer outside of the trench defines a drift region.

12. The integrated circuit device of claim 1, wherein the first doping type is a p-type and the second doping type is an n-type.

13. An integrated circuit device, comprising:

a substrate;

a pad layer supported by the substrate, the pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type;

a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion;

a gate formed in the trench and over a portion of a top surface of the pad layer, the gate extending along the interface of the body portion and the drift region portion;

a dielectric material formed in the trench on opposing sides of the gate; and

a field plate material embedded in the dielectric material on both a source side and a drain side of the gate, the field plate material on the drain side of the gate configured to function as a field plate.

14. The integrated circuit device of claim 13, wherein one of an insulator layer and a buried layer having the first doping type is interposed between the substrate and the pad layer.

15. The integrated circuit device of claim 13, wherein a source is at least partially formed using the trench.

16. The integrated circuit device of claim 13, wherein a longest dimension of the trench is orthogonal to the interface and a longest dimension of the gate.

17. The integrated circuit device of claim 13, the dielectric material formed in the trench is disposed on trench sidewalls, a trench floor, and gate sidewalls.

18. A method of forming a fin field effect transistor (FinFET) device, comprising:

forming a trench in a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, the trench extending through an interface of the body portion and the drift region portion;

forming a gate in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion;

depositing a dielectric material in the trench on opposing sides of the gate; and

embedding a field plate in the dielectric material on one of the opposing sides of the gate.

19. The method of claim 18, further comprising forming a source using the trench.

20. The method of claim 18, further comprising orienting a longest dimension of the trench orthogonal to a longest dimension of the gate.