REDUCING SOURCE LOADING EFFECT IN SPIN TORQUE TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY (STT-MRAM)

• US 20140015077A1
• Filed: 09/16/2013
• Published: 01/16/2014
• Est. Priority Date: 03/02/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lee, Kangho, Kang, Seung H., Zhu, Xiaochun
• Granted Patent: US 9,105,340 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A memory cell comprises a magnetic tunnel junction (MTJ) structure that includes a free layer coupled to a bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. The pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

Claims

1. An apparatus comprising:

a memory cell comprising;

a magnetic tunnel junction (MTJ) structure including;

a free layer coupled to a bit line; and

a pinned layer, wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state,

wherein the pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

2. The apparatus of claim 1, wherein the first switching current is less than a first threshold associated with an operating current characteristic of the access transistor, and wherein the operating current characteristic of the access transistor comprises a current from a drain terminal of the access transistor to a source terminal of the access transistor at a predetermined voltage between a gate terminal of the access transistor and the drain terminal of the access transistor.

3. The apparatus of claim 1, wherein the free layer is positioned a first distance from the drain terminal and the pinned layer is positioned a second distance from the drain terminal, the first distance greater than the second distance, and wherein a conductive path electrically connects the drain terminal to the free layer.

4. The apparatus of claim 1, wherein the free layer is positioned a first distance from drain terminal and the pinned layer is positioned a second distance from the drain terminal, the second distance greater than the first distance, and wherein a conductive path electrically connects the drain terminal to the free layer.

5. The apparatus of claim 1 integrated in at least one semiconductor die.

6. The apparatus of claim 1, further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the memory cell is integrated.

7. An apparatus comprising:

means for storing a data value as an orientation of a magnetic moment that is programmable by a spin polarized current exceeding a threshold current density, the means for storing the data value coupled to a bit line; and

means for storing a pinned magnetic moment having a pinned orientation, wherein the magnetic moment that is programmable is substantially parallel to the pinned magnetic moment in a first state and substantially antiparallel to the pinned magnetic moment in a second state,

wherein the means for storing the pinned magnetic moment has a physical dimension to produce an offset magnetic field corresponding to a first switching current to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

8. The apparatus of claim 7 integrated in at least one semiconductor die.

9. The apparatus of claim 7, further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the means for storing the data value and the means for storing the pinned magnetic moment are integrated.

10. An apparatus comprising:

a memory device comprising;

a plurality of memory cells, wherein at least one memory cell of the plurality of memory cells comprises;

a magnetic tunnel junction (MTJ) structure, wherein a magnetic moment of a free layer of the MTJ structure is substantially parallel to a magnetic moment of a pinned layer of the MTJ structure in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state; and

an access transistor coupled to the MTJ structure,

wherein a ratio of a magnitude of a first switching current to switch the MTJ structure from the first state to the second state is less than half of a second switching current to switch the MTJ structure from the second state to the first state.

11. The apparatus of claim 10 integrated in at least one semiconductor die.

12. The apparatus of claim 10, further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the memory device is integrated.

13. A method comprising:

receiving design information representing at least one physical property of a semiconductor device, the semiconductor device including a magnetic tunnel junction (MTJ) structure including;

a free layer coupled to a bit line; and

a pinned layer, wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state,

wherein the pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line;

transforming the design information to comply with a file format; and

generating a data file including the transformed design information.

14. The method of claim 13, wherein the data file includes a GDSII format.

15. A method comprising:

receiving a data file including design information corresponding to a semiconductor device; and

fabricating the semiconductor device according to the design information, wherein the semiconductor device includes a magnetic tunnel junction (MTJ) structure including;

a free layer coupled to a bit line; and

a pinned layer, wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state,

wherein the pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

16. The method of claim 15, wherein the data file has a GDSII format.

17. A method comprising:

receiving design information including physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device including a semiconductor structure comprising a magnetic tunnel junction (MTJ) structure including;

a free layer coupled to a bit line; and

a pinned layer, wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state,

wherein the pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line; and

transforming the design information to generate a data file.

18. The method of claim 17, wherein the data file has a GERBER format.

19. A method comprising:

receiving a data file including design information including physical positioning information of a packaged semiconductor device on a circuit board; and

manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises a magnetic tunnel junction (MTJ) structure including;

a free layer coupled to a bit line; and

a pinned layer, wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state,

wherein the pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

20. The method of claim 19, wherein the data file has a GERBER format.

21. The method of claim 19, further comprising integrating the circuit board into a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.