CONTACT MEMS ARCHITECTURE FOR IMPROVED CYCLE COUNT AND HOT-SWITCHING AND ESD

• US 20140015731A1
• Filed: 07/11/2013
• Published: 01/16/2014
• Est. Priority Date: 07/11/2012
• Status: Abandoned Application

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Khlat, Nadim, Hammond, Jonathan Hale
• Application Number:
  US13/939,941
• Publication Number:
  US 20140015731A1
• Time in Patent Office: Days
• US Class Current: 343/876
• CPC Class Codes: H01H 1/0036 Switches making use of microelectromechanical systems [MEMS] for electromagnetic relays H01H50/005; for electrostatic relays H01H59/0009
• CPC Class Codes: H01H 9/548 Electromechanical and static switch connected in series
• CPC Class Codes: H01Q 1/50 Structural association of antennas with earthing switches, lead-in devices or lightning protectors
• CPC Class Codes: H01Q 21/0006 Particular feeding systems
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

The disclosure is directed to optimized switching circuitry utilizing MEMS (Microelectromechanical Systems) circuitry in series with solid state circuitry. Specifically, the MEMS circuitry includes a first MEMS circuit in parallel with (and separate from) a second MEMS circuit. A paired signal is defined as a transmit signal and a receive signal (in a single band) that are transmitted or received on separate paths or on separate nodes. The transmit signal is associated with the first MEMS circuit, and the receive signal is associated with the second MEMS circuit. The solid state circuitry switches between the first MEMS circuit and second MEMS circuit without requiring any switching in the first or second MEMS circuits.

Claims

1. Optimized switching circuitry comprising:

MEMS (Microelectromechanical Systems) circuitry including a first MEMS circuit and a second MEMS circuit, wherein the first MEMS circuit and the second MEMS circuit are in parallel with each other; and

solid state circuitry in series with the MEMS circuitry.

2. The optimized switching circuitry of claim 1, further comprising:

a first signal pair of nodes in a first band,

wherein the first signal pair of nodes includes a first transmit signal node and a first receive signal node,

wherein the first transmit signal node is associated with the first MEMS circuit, and

wherein the first receive signal node is associated with the second MEMS circuit.

3. The optimized switching circuitry of claim 2, wherein the solid state circuitry includes SOI (Silicon-On-Insulator) circuitry.

4. The optimized switching circuitry of claim 2, wherein the solid state circuitry is configured to quickly switch back and forth between the first MEMS circuit and the second MEMS circuit, thereby quickly switching back and forth between the first transmit signal node and the first receive signal node without requiring any MEMS switching.

5. The optimized switching circuitry of claim 4, further comprising

a second signal pair of nodes including a second transmit signal node and a second receive signal node,

wherein the second transmit signal node is associated with the first MEMS circuit, and wherein the second receive signal node is associated with the second MEMS circuit.

6. The optimized switching circuitry of claim 4, further comprising

a second signal pair of nodes including a second transmit signal node and a second receive signal node, wherein the second transmit signal node is associated with the second MEMS circuit, and wherein the second receive signal node is associated with the first MEMS circuit.

7. The optimized switching circuitry of claim 4,

wherein the first MEMS circuit includes a SPNT (Single Pole, N Throws) MEMS switch,

wherein a first throw of the N throws is associated with the first transmit signal node;

wherein a second throw of the N throws is associated with the second transmit signal node;

wherein the second MEMS circuit includes a SPMT (Single Pole, M Throws) MEMS switch;

wherein a first throw of the M throws is associated with the first receive signal node; and

wherein a second throw of the M throws is associated with the second receive signal node;

8. The optimized switching circuitry of claim 7,

wherein the solid state circuitry includes a SPLT (Single Pole, L Throws) solid state switch;

wherein a first throw of the L throws is associated with the single pole of the first MEMS circuit;

wherein a second throw of the L throws is associated with the single pole of the second MEMS circuit;

wherein the single pole of the solid state circuitry is associated with an antenna.

9. The optimized switching circuitry of claim 8, wherein the solid state circuitry includes SOI (Silicon-On-Insulator) circuitry.

10. The optimized switching circuitry of claim 8, further comprising:

a controller,

wherein the controller is configured to switch the solid state circuitry and to switch the MEMS circuitry.

11. The optimized switching circuitry of claim 10, wherein the controller is configured to cause the following steps to occur:

during a first period;

set the solid state circuitry to communicate with the first transmit signal node through the first MEMS circuit;

during a second period;

switch the solid state circuitry to communicate with the first receive signal node through the second MEMS circuit without switching any MEMS switch in the MEMS circuitry;

during a third period;

set switch solid state circuitry to communicate with the first transmit signal node through the first MEMS circuit, then switch OFF a MEMS switch associated with the first receive signal node, then switch ON a MEMS switch associated with the second receive signal node;

during a fourth period;

switch the solid state circuitry to communicate with the second receive signal node, then switch OFF a MEMS switch associated with the first transmit signal node, then switch ON a MEMS switch associated with the second transmit signal node;

during a fifth period;

switch the solid state circuitry to communicate with the second transmit signal node;

during a sixth period;

switch the solid state circuitry to communicate with the second receive signal node.

12. The optimized switching circuitry of claim 10, wherein the controller is configured to cause the following steps to occur:

a) switch the MEMS circuitry so that;

the first transmit signal node is selected by the first MEMS circuit, the first receive signal node is selected by the second MEMS circuit, and the first MEMS circuit is selected by the solid state circuitry;

b) switch the second MEMS circuit to deselect the first receive signal node;

c) switch the second MEMS circuit to select the second receive signal node;

d) switch the solid state circuitry to select the second MEMS circuit;

e) switch the first MEMS circuit to deselect the first transmit signal node; and

f) switch the first MEMS circuit to select the second transmit signal node.

13. The optimized switching circuitry of claim 8, further comprising a bidirectional coupler located between the solid state circuitry and a first antenna.

14. The optimized switching circuitry of claim 13, further comprising a measurement semiconductor circuit configured to receive bidirectional power information from the bidirectional coupler.

15. The optimized switching circuitry of claim 14, wherein the MEMS circuitry further includes a third MEMS circuit, and wherein the third MEMS circuit is configured to route at least the first transmit signal node to a second antenna.

16. Optimized switching circuitry comprising:

MEMS circuitry including an SPNT MEMS switch, wherein the SPNT MEMS switch is configured to select one out of at least two signal nodes, and to route the selected signal node to an antenna; and

solid state circuitry in parallel with the MEMS circuitry, wherein the solid state circuitry includes a SPMT solid state switch, and wherein the SPMT solid state switch is configured to select one out of at least two additional signal nodes, and to route the selected additional signal node to the antenna.

17. The optimized switching circuitry of claim 16, wherein the solid state circuitry includes a controller configured to control the SPNT MEMS switch and the SPMT solid state switch.

18. The optimized switching circuitry of claim 17, wherein the controller controls the SPNT MEMS switch via control lines.

19. The optimized switching circuitry of claim 17, further comprising:

a pilot switch configured to ground the antenna upon receiving a command from the controller.

20. The optimized switching circuitry of claim 19, wherein the controller is configured to control the SPNT MEMS switch, the SPMT solid state switch, and the pilot switch by causing the following steps to be performed:

during a first period;

switch the solid state circuitry to select a first solid state signal node, then switch the solid state circuitry to deselect the first solid state signal node and to select a second solid state signal node;

during a second period;

switch the pilot switch to ground the antenna, then switch the MEMS circuitry to select a first MEMS signal node, then switch the pilot switch to isolate the antenna from a ground;

during a third period;

switch the pilot switch to ground the antenna, then switch the MEMS circuitry to deselect a first MEMS signal node and to select a second MEMS signal node, then switch the pilot switch to isolate the antenna from a ground;

during a fourth period;

switch the pilot switch to ground the antenna, then switch the MEMS circuitry to deselect the second MEMS signal node, then switch the pilot switch to isolate the antenna from a ground; and

during a fifth period;

switch the solid state circuitry to select the first solid state signal node, then switch the solid state circuitry to deselect the first solid state signal node and to select a second solid state signal node.