Controlling A Plurality Of Serial Peripheral Interface ('SPI') Peripherals Using A Single Chip Select

• US 20140019644A1
• Filed: 07/10/2012
• Published: 01/16/2014
• Est. Priority Date: 07/10/2012
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Decesaris, Michael, Remis, Luke D., Sellman, Gregory D., Vanderlinden, Steven L.
• Granted Patent: US 9,411,770 B2
• Time in Patent Office: Days
• US Class Current: 710/5
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.

Claims

1. A method of controlling a plurality of serial peripheral interface (‘

SPI’

) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, the method comprising;

receiving, by the first SPI peripheral, a signal from the SPI master;

determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral;

responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and

responsive to determining that the first SPI peripheral is the primary SPI peripheral;

servicing, by the first SPI peripheral, an instruction contained in the signal; and

transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.

2. The method of claim 1 further comprising:

receiving, by the second SPI peripheral, a signal from the first SPI peripheral;

determining, by the second SPI peripheral, whether the second SPI peripheral is the primary SPI peripheral or the backup SPI peripheral;

responsive to determining that the second SPI peripheral is the backup SPI peripheral, transmitting, by the second SPI peripheral to the SPI master, the signal from the first SPI peripheral; and

responsive to determining that the second SPI peripheral is the primary SPI peripheral;

servicing, by the second SPI peripheral, an instruction contained in the signal from the first SPI peripheral; and

transmitting, by the second SPI peripheral to the SPI master, a response signal.

3. The method of claim 1 wherein determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral includes receiving, by the first SPI peripheral, a polarity signal.

4. The method of claim 2 wherein determining, by the second SPI peripheral, whether the second SPI peripheral is a primary SPI peripheral or a backup SPI peripheral includes receiving, by the second SPI peripheral, a polarity signal.

5. The method of claim 1 wherein the signal from the SPI master is received by the first SPI peripheral via a signal line coupling a master out, slave in (‘

MOSI’

) interface of the first SPI peripheral to the SPI master.

6. The method of claim 1 wherein the signal from the first SPI peripheral is transmitted to the second SPI peripheral via a signal line coupling a master in, slave out (‘

MISO’

) interface of the first SPI peripheral to a MOSI interface of the second SPI peripheral.

7. The method of claim 1 wherein the each SPI peripheral is an option ROM.

8. The method of claim 2 wherein only one SPI peripheral is the primary SPI peripheral.

9. The method of claim 2 wherein only one SPI peripheral is the backup SPI peripheral.

10. An apparatus for controlling a plurality of serial peripheral interface (‘

SPI’

) peripherals using a single chip select in a computing system, the apparatus including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, wherein the first SPI peripheral carries out the steps of;

receiving a signal from the SPI master;

determining whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral;

responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, to the second SPI peripheral, the signal; and

responsive to determining that the first SPI peripheral is the primary SPI peripheral;

servicing an instruction contained in the signal; and

transmitting, to the second SPI peripheral, a response signal.

11. The apparatus of claim 10 wherein the second SPI peripheral carries out the steps of:

receiving a signal from the first SPI peripheral;

determining whether the second SPI peripheral is the primary SPI peripheral or the backup SPI peripheral;

responsive to determining that the second SPI peripheral is the backup SPI peripheral, transmitting, to the SPI master, the signal from the first SPI peripheral; and

responsive to determining that the second SPI peripheral is the primary SPI peripheral;

servicing, by the second SPI peripheral, an instruction contained in the signal from the first SPI peripheral; and

transmitting, to the SPI master, a response signal.

12. The apparatus of claim 10 wherein determining whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral includes receiving, by the first SPI peripheral, a polarity signal.

13. The apparatus of claim 11 wherein determining whether the second SPI peripheral is a primary SPI peripheral or a backup SPI peripheral includes receiving, by the second SPI peripheral, a polarity signal

14. The apparatus of claim 10 wherein the signal from the SPI master is received by the first SPI peripheral via a signal line coupling a master out, slave in (‘

MOSI’

) interface of the first SPI peripheral to the SPI master

15. The apparatus of claim 11 wherein the signal from the first SPI peripheral is transmitted to the second SPI peripheral via a signal line coupling a master in, slave out (‘

MISO’

) interface of the first SPI peripheral to a MOSI interface of the second SPI peripheral.

16. The apparatus of claim 10 wherein the each SPI peripheral is an option ROM.

17. The apparatus of claim 11 wherein only one SPI peripheral is the primary SPI peripheral.

18. The apparatus of claim 11 wherein only one SPI peripheral is the backup SPI peripheral.