System and Method for Providing Network Access for a Processing Node

• US 20140019661A1
• Filed: 05/17/2013
• Published: 01/16/2014
• Est. Priority Date: 05/18/2012
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Hormuth, Robert W., Winter, Robert L., Dube, Shawn J., Booth, Bradley J., Lin, Geng, Pike, Jimmy
• Granted Patent: US 9,442,876 B2
• Time in Patent Office: Days
• US Class Current: 710/306
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 15/17331 Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
• CPC Class Codes: G06F 21/572 Secure firmware programming, e.g. of basic input output system [BIOS]
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 41/06 Management of faults, events, alarms or notifications
• CPC Class Codes: H04L 49/00 Packet switching elements
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A network interface controller includes a plurality of host interfaces configured to communicate with a plurality of processing nodes, a plurality of network interfaces configured to provide network communication for the processing nodes to a network, and a shared resource configured to provide link based services and stateless offload services for the processing nodes when communicating with the network.

Claims

1. A network interface controller comprising:

a plurality of host interfaces configured to communicate with a plurality of processing nodes;

a plurality of network interfaces configured to provide network communication for the processing nodes to a network; and

a shared resource configured to provide link based services and stateless offload services for the processing nodes when communicating with the network.

2. The network interface controller of claim 1, wherein the plurality of host interfaces comprise Peripheral Component Interconnect-Express (PCIe) interfaces.

3. The network interface controller of claim 1, wherein the plurality of network interfaces each comprise a Media Access Control (MAC) layer and a physical (PHY) layer.

4. The network interface controller of claim 3, wherein the PHY layer comprises an Ethernet PHY.

5. The network interface controller of claim 1, wherein the shared resource comprises:

a buffer and queue block;

a link based services block;

a stateless offload services block;

a storage block; and

a management block.

6. The network interface controller of claim 5, wherein the buffer and queue block comprises a plurality of buffers and queues, each of the plurality of buffers and queues being associated with a respective network interface of the plurality of network interfaces.

7. The network interface controller of claim 6, wherein further the plurality of buffers and queues implement priority queues for network traffic for the plurality of network interfaces.

8. The network interface controller of claim 6, wherein the plurality of buffers and queues is dynamically allocated between the plurality of network interfaces.

9. The network interface controller of claim 5, wherein the link based services block provides priority based flow control for the plurality of network interfaces.

10. The network interface controller of claim 5, wherein the link based services block provides congestion notification for the plurality of network interfaces.

11. The network interface controller of claim 5, wherein the stateless offload services block provides at least one of a TCP segmentation offload, an IP checksum offload, Receive Side Scaling (RSS), and Large Send Offload (LSO).

12. The network interface controller of claim 5, wherein the storage block stores a firmware that is common to the plurality of network interfaces.

13. The network interface controller of claim 5, wherein the storage block stores network destination information for the plurality of network interfaces.

14. The network interface controller of claim 13, wherein the network destination information comprises at least one of a unified address resolution protocol table and a neighbor discovery protocol table.

15. The network interface controller of claim 5, wherein the management block provides set-up and tear-down services for the plurality of network interfaces.

16. The network interface controller of claim 1, wherein the network interface controller supports an Open Fabrics alliance Enterprise Distribution (OFED) verbs Application Programming Interface (API).

17. The network interface controller of claim 16, wherein the network interface controller further supports a Peripheral Component Interconnect-Express (PCIe) Transaction Layer Packet/Data Link Packet (TLP/DLP) interconnect.

18. A network interface controller comprising:

a first network interface configured to provide network communication for a first processing node, the first network interface comprising;

a first transmit buffer configured to buffer data packets being sent by the first processing node;

a first receive buffer configured to buffer data packets being received by the first processing node; and

a first network link configured to send and receive communication between the first processing node with the network;

a second network interface configured to provide network communication for a second processing node, the second network interface comprising;

a second transmit buffer configured to buffer data packets being sent by the second processing node;

a second receive buffer configured to buffer data packets being received by the second processing node; and

a second network link configured to send and receive communication between the second processing node with the network; and

a buffer manager configured to write a first data packet directly from the first transmit buffer to the second receive buffer bypassing the first network link.

19. The network interface controller of claim 18, wherein in writing the first data packet directly from the first transmit buffer to the second receive buffer, the buffer manager is further configured to provide a direct memory access between the first processing node and the second processing node.

20. The network interface controller of claim 18, wherein the direct memory access between the first processing node and the second processing node is over a Peripheral Component Interconnect-Express (PCIe) path.

21. The network interface controller of claim 18, wherein the buffer manager is further configured to write a second data packet directly from the second transmit buffer to the first receive buffer bypassing the second network link.

22. A network interface controller comprising:

a first queue configured to store communication data from a first processing node to a second processing node;

a second queue configured to store communication data from the second processing node to the first processing node;

a first network interface configured to;

write data packets from the first processing node to the second queue when there are empty locations within the second queue;

read data packets from the first queue when the number of ‘

to be processed’

entries exceeds a minimum number of ‘

to be processed’

entries;

delay writing data packets from the first processing node to the second queue when the number of empty locations within the second queue is below a threshold; and

delay reading data packets from the first queue when the number of ‘

to be processed’

entries is below the minimum number of ‘

to be processed’

entries.