METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA
First Claim
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1. A processor, comprising:
- a cache memory to store data;
a memory controller to provide access to an external random access memory;
a plurality of processing cores in a single chip package, wherein each processing core is to execute multiple threads simultaneously, and wherein each processing core further comprises;
instruction fetch logic to fetch one or more instructions;
instruction decode logic to decode one or more instructions;
a register file including a set of vector registers, each vector register to store a plurality of vector data elements;
an execution unit to execute a first instruction to read a single-precision floating point value from memory, convert the value to a double-precision floating point value, store the results in a vector register of the register file,wherein the execution unit is to execute a second instruction to convert a single-precision floating point value to a signed integer value and store the results in a storage location,and wherein the execution unit is to execute a third instruction to convert a single-precision floating point value to an unsigned integer value and store the results in the storage location.
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Abstract
A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.
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Citations
4 Claims
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1. A processor, comprising:
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a cache memory to store data; a memory controller to provide access to an external random access memory; a plurality of processing cores in a single chip package, wherein each processing core is to execute multiple threads simultaneously, and wherein each processing core further comprises; instruction fetch logic to fetch one or more instructions; instruction decode logic to decode one or more instructions; a register file including a set of vector registers, each vector register to store a plurality of vector data elements; an execution unit to execute a first instruction to read a single-precision floating point value from memory, convert the value to a double-precision floating point value, store the results in a vector register of the register file, wherein the execution unit is to execute a second instruction to convert a single-precision floating point value to a signed integer value and store the results in a storage location, and wherein the execution unit is to execute a third instruction to convert a single-precision floating point value to an unsigned integer value and store the results in the storage location. - View Dependent Claims (2, 3, 4)
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Specification
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Current AssigneeAnwar Rohillah, Douglas M. Carmean, Eric Sprangle, Robert D. Cavin
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Original AssigneeAnwar Rohillah, Douglas M. Carmean, Eric Sprangle, Robert D. Cavin
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InventorsSprangle, Eric, Cavin, Robert D., Rohillah, Anwar, Carmean, Douglas M.
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Application NumberUS13/762,220Publication NumberTime in Patent OfficeDaysField of SearchUS Class Current712/206CPC Class CodesG06F 9/30025 Format conversion instructi...G06F 9/30036 Instructions to perform ope...G06F 9/30043 LOAD or STORE instructions;...
