PROCESS-COMPATIBLE DECOUPLING CAPACITOR AND METHOD FOR MAKING THE SAME

• US 20140021584A1
• Filed: 07/19/2012
• Published: 01/23/2014
• Est. Priority Date: 07/19/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tu, Kuo-Chi, Chu, Wen-Ting
• Granted Patent: US 8,896,096 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Provided is decoupling capacitor device. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.

Claims

1. A decoupling capacitor device comprising:

a bottom electrode;

a first dielectric layer portion located above, and in physical contact with, the bottom electrode, the first dielectric layer portion being deposited in a dielectric layer deposition process that also deposits a second dielectric layer portion in a non-volatile memory (NVM) cell, the first and second dielectric layer portions being patterned by a single mask; and

a top electrode located above, and in physical contact with, the first dielectric layer portion such that the top electrode, the first dielectric layer, and the bottom electrode form a decoupling capacitor.

2. The device of claim 1, wherein the second dielectric layer portion forms an insulator layer in a metal-insulator-metal (MIM) structure in the NVM cell, the MIM structure further comprising a bottom MIM electrode and a top MIM electrode, the bottom MIM electrode formed from a first metal layer deposited by a first metal process, the bottom electrode also being formed from the first metal layer, and the top MIM electrode formed from a second metal layer deposited by a second metal process, the top electrode also being formed from the second metal layer.

3. The device of claim 1, wherein the dielectric layer deposition process deposits a dielectric layer comprising at least one of NiO, TiO, HfO, ZrO, ZnO, WO₃, Al₂O₃, TaO, MoO, and CuO.

4. The device of claim 2, wherein:

the first metal layer comprises at least one of Pt, AlCu, TiN, Au, Ti, Ta, TaN, W, WN, and Cu; and

the second metal layer comprises at least one of Pt, AlCu, TiN, Au, Ti, Ta, TaN, W, WN, and Cu.

5. The device of claim 1, wherein the capacitor is one of a planar-type capacitor, a cylinder-type capacitor, a bar-type capacitor, and a capacitor formed by a dual-damascene process.

6. A system-on-chip (SOC) device comprising:

a resistive random-access memory (RRAM) cell, the RRAM cell including a metal-insulator-metal (MIM) structure, the MIM structure comprising a bottom MIM electrode, a MIM insulating layer, and a top MIM electrode, the MIM structure being situated in an inter-metal dielectric layer;

a decoupling capacitor, the decoupling capacitor comprising a bottom capacitor electrode, a capacitor insulating layer, and a top capacitor electrode, the decoupling capacitor situated in the inter-metal dielectric layer; and

a logic area comprising a plurality of transistors on a substrate.

7. The SOC device of claim 6, wherein the bottom MIM electrode and the bottom capacitor electrode are formed from a first process, the MIM insulating layer and the capacitor insulating layer are formed from a second process, and the top MIM electrode and the top capacitor electrode are formed from a third process.

8. The SOC device of claim 7, wherein the MIM structure and the decoupling capacitor are formed using a single mask.

9. The SOC device of claim 8, further comprising a plurality of inter-metal dielectric layers, the decoupling capacitor and the MIM structure being situated in one layer of the plurality of inter-metal dielectric layers.

10. The SOC device of claim 8, wherein a portion of the logic area is situated below the decoupling capacitor, but is not in electrically-conducting contact with the decoupling capacitor.

11. The SOC device of claim 7, wherein the decoupling capacitor comprises a plurality of decoupling capacitors, wherein each of the plurality of decoupling capacitors comprises a bottom capacitor electrode, a capacitor insulating layer, and a top capacitor electrode, all of the plurality of decoupling capacitors being situated in the inter-metal dielectric layer and formed from a single mask.

12. The SOC device of claim 8, further comprising a volatile memory cell, the volatile memory cell including a capacitive memory element formed using the single mask and that has a bottom capacitive element electrode formed from the first process, a capacitive insulating layer formed from the second process, and a top capacitive electrode formed from the third process.

13. The SOC device of claim 12, wherein the volatile memory cell is a dynamic random-access memory (DRAM) cell.

14. A method for forming a process-compatible decoupling capacitor, the method comprising:

forming a bottom electrode layer above, and in electrical contact with, a metal layer;

forming an insulating layer above the bottom electrode layer;

forming a top electrode layer above the insulating layer; and

patterning the top electrode layer, the insulating layer, and the bottom electrode layer to form a metal-insulator-metal (MIM) structure of a non-volatile memory element and to form a decoupling capacitor.

15. The method of claim 14, wherein patterning the top electrode, insulating, and bottom electrode layers comprises using a single mask to form the MIM structure and the decoupling capacitor.

16. The method of claim 14, wherein the MIM element and the decoupling capacitor are situated on substantially the same level, the level being defined by an inter-metal dielectric layer.

17. The method of claim 14, wherein:

forming the bottom electrode layer and forming the top electrode layer each comprise depositing a layer of one of Pt, AlCu, TiN, Au, Ti, Ta, TaN, W, WN, and Cu; and

forming the insulating layer further comprises depositing a layer of one of NiO, TiO, HfO, ZrO, ZnO, WO₃, Al₂O₃, TaO, MoO, and CuO.

18. The method of claim 15, further comprising patterning the top electrode layer, the insulating layer, and the bottom electrode layer to form a capacitive memory element of a DRAM cell also using the single mask.

19. The method of claim 14, wherein the bottom electrode, insulating, and top electrode layers are formed in between a top of a third metallization layer and a top of a fourth metallization layer, the third metallization layer being the metal layer.

20. The method of claim 14, wherein the bottom electrode, insulating, and top electrode layers are formed in between a top of a fourth metallization layer and a top of a fifth metallization layer, the fourth metallization layer being the metal layer.