SEMICONDUCTOR DEVICE

• US 20140021637A1
• Filed: 09/25/2013
• Published: 01/23/2014
• Est. Priority Date: 05/18/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Rieger, Walter, Hirler, Franz, Poelzl, Martin, Kotek, Manfred
• Granted Patent: US 9,754,859 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a semiconductor substrate, a doped zone, a polysilicon layer and an elongate plug structure. The doped zone is within the semiconductor substrate. The polysilicon layer is disposed in a trench electrically isolated from the semiconductor substrate by an insulating layer. The elongate plug structure extends in a lateral direction in or above the semiconductor substrate. The elongate plug structure provides electrical connection between the doped zone and the polysilicon layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a doped zone within the semiconductor substrate;

a polysilicon layer in a trench electrically isolated from the semiconductor substrate by an insulating layer; and

an elongate plug structure extending in a lateral direction in or above the semiconductor substrate, the elongate plug structure providing electrical connection between the doped zone and the polysilicon layer.

2. The semiconductor device of claim 1, wherein a bottom side of the elongate plug structure abuts on each one of the doped zone, the insulating layer and the polysilicon layer.

3. The semiconductor device of claim 1, further comprising a plurality of plug structures.

4. The semiconductor device of claim 3, wherein the plug structures are laterally oriented trenches filled with polysilicon.

5. The semiconductor device of claim 3, wherein the plug structures are laterally oriented trenches filled with tungsten.

6. The semiconductor device of claim 3, wherein the plug structures provide electrical lines operable to carry lateral current flows within a cell array, within an edge region or within a logic region of the semiconductor device.

7. The semiconductor device of claim 6, wherein the plug structures make contact with semiconductor zones of the cell array.

8. The semiconductor device of claim 7, wherein the plug structures are positioned at least in part directly on the semiconductor zones of the cell array.

9. The semiconductor device of claim 7, wherein the plug structures are connected at least in part by the semiconductor zones of the cell array.

10. The semiconductor device of claim 7, wherein the plug structures are isolated at least in part from the semiconductor zones of the cell array by an insulation layer.

11. The semiconductor device of claim 7, wherein a first portion of the plug structures forms a vertical electrical connection between semiconductor zones and a metallization layer arranged thereabove, and a second portion of the plug structures forms an electrical line for a lateral current flow.

12. The semiconductor device of claim 7, wherein the plug structures form an electrical connection between a semiconductor zone and a conductive layer which runs within a trench formed in the semiconductor zone.

13. A semiconductor device comprising:

a semiconductor substrate, and

an insulating layer on the semiconductor substrate;

a polysilicon layer on the insulating layer;

a doped zone within the semiconductor substrate; and

an elongate plug structure extending in a lateral direction above the semiconductor substrate, the elongate plug structure providing electrical connection between the doped zone and the polysilicon layer.

14. The semiconductor device of claim 13, further comprising a plurality of plug structures.

15. The semiconductor device of claim 14, wherein the plug structures provide electrical lines operable to carry lateral current flows within a cell array, within an edge region or within a logic region of the semiconductor device.

16. The semiconductor device of claim 14, wherein the plug structures make contact with semiconductor zones of the cell array.

17. The semiconductor device of claim 14, wherein a first portion of the plug structures forms a vertical electrical connection between semiconductor zones and a metallization layer arranged thereabove, and a second portion of the plug structures forms an electrical line for a lateral current flow.