THERMAL MANAGEMENT OF TIGHTLY INTEGRATED SEMICONDUCTOR DEVICE, SYSTEM AND/OR PACKAGE

• US 20140022002A1
• Filed: 01/15/2013
• Published: 01/23/2014
• Est. Priority Date: 07/20/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chua-Eoan, Lew G., Zhang, Ronglian
• Granted Patent: US 9,508,607 B2
• Time in Patent Office: Days
• US Class Current: 327/512
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G07F 17/326 Game play aspects of gaming systems
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
• CPC Class Codes: H01L 22/10 Measuring as part of the manufacturing process burn-in G01R31/2855
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/345 Arrangements for heating thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H10N 10/00 Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects integrated devices or assemblies of multiple devices H10N19/00
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Some implementations provide a semiconductor package that includes a first die and a second die adjacent to the first die. The second die is capable of heating the first die. The semiconductor package also includes a leakage sensor configured to measure a leakage current of the first die. The semiconductor package also includes a thermal management unit coupled to the leakage sensor. The thermal management unit configured to control a temperature of the first die based, on the leakage current of the first die.

Claims

1. A semiconductor package comprising:

a first die;

a second die adjacent to the first die, the second die capable of heating the first die;

a leakage sensor configured to measure a leakage current of the first die; and

a thermal management unit coupled to the leakage sensor, the thermal

management unit configured to control a temperature of the first die based on the

leakage current of the first die.

2. The semiconductor package of claim 1, wherein the thermal management unit is configured, to control the temperature of the first die by controlling heat emanating from the second die based on the leakage current of the first die.

3. The semiconductor package of claim 2, wherein controlling the heat emanating from the second die comprises reducing activity of the second die based on the leakage current of the first die.

4. The semiconductor package of claim 1, wherein the leakage sensor configured to measure the the leakage current is a sensor configured, to measure a voltage drop in the first die.

5. The semiconductor package of claim 1, wherein the first die has a thermal tolerance, the thermal management unit is configured to control the temperature of the first die by controlling heat emanating from the second die based, on the thermal tolerance of the first die.

6. The semiconductor package of claim 5, wherein controlling the heat emanating from the second die based on the thermal tolerance of the first die comprises determining the temperature of the first die based on the measured leakage current of the first die and comparing the measured temperature to the thermal tolerance of the first die.

7. The semiconductor package of claim 1 further comprising a heat reducing mechanism coupled to the thermal management unit.

8. The semiconductor package of claim 7, wherein the first die is a memory and the heat reducing mechanism is a memory controller.

9. The semiconductor package of claim 7, wherein the heat reducing mechanism reduces heat by performing one of at least Dynamic Voltage and Frequency Scaling (DVFS), Dynamic Frequency Scaling (DFS), clock gating, and power collapsing.

10. The semiconductor package of claim 1, wherein the leakage sensor is separate from the first die.

11. The semiconductor package of claim 1, wherein the leakage sensor is part of the first die.

12. The semiconductor package of claim 1, wherein the thermal management unit is part of the second die.

13. The semiconductor package of claim 1, wherein the first die is stacked on top of the second die.

15. The semiconductor package of claim 1, wherein the first die, the second die and the thermal management unit are part of at least one of a System in Package (SiP) and System on Glass (SoG),

16. The semiconductor package of claim 1, wherein the package is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

14. The semiconductor package of claim i, wherein the first die and the second die are coupled to each other by through substrate vias (TSVs).

17. An apparatus comprising:

a first die;

a second die adjacent to the first die, the second die capable of heating the first die;

means for measuring a leakage current of the first die; and

means for controlling a temperature of the first die based on the leakage current of the first die,

18. The apparatus of claim 17, wherein the means for controlling the temperature of the first die is a means for controlling heat emanating from the second die based on the leakage current of the first die.

19. The apparatus of claim 18, wherein means for controlling the heat emanating from the second die comprises a means for reducing activity of the second, die based on the leakage current of the first die.

20. The apparatus of claim 17, wherein the means for measuring the leakage current is a means for measuring a voltage drop in the first die.

21. The apparatus of claim 17, wherein the first die has a thermal tolerance, the means for controlling the temperature of the first die comprises a means for controlling heat emanating from the second, die based on the thermal tolerance of the first die.

22. The apparatus of claim 21, wherein the means for controlling the heat emanating from the second die based on the thermal tolerance of the first die comprises means for determining the temperature of the first die based on the measured leakage current of the first die and means for comparing the measured temperature to the thermal tolerance of the first die.

23. The apparatus of claim 17 further comprising a means for a heat reducing mechanism.

24. The apparatus of claim 23, wherein the first die is a memory and. the means for the heat reducing mechanism is a memory controller.

25. The apparatus of claim 23, wherein the means for the heat reducing mechanism reduces heat by performing one of at least Dynamic Voltage and Frequency Scaling (DVFS), Dynamic Frequency Scaling (DFS), clock gating, and power collapsing.

26. The apparatus of claim 17, wherein the apparatus is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

27. A method for manufacturing a semiconductor package encapsulating several dice, the method comprising:

positioning a first die on a packaging substrate;

positioning a second die adjacent to the first die, the second die capable of heating the first die;

positioning a leakage sensor within the package, the leakage sensor configured, to measure a leakage current of the first die; and

positioning a thermal management unit within the package, the thermal management unit coupled to the leakage sensor, the thermal management unit configured to control a temperature of the first die based on the leakage current of the first die.

28. The method of claim 27, wherein the thermal management unit is configured to control the temperature of the first die by controlling heat emanating from the second, die based on the leakage current of the first die.

29. The method of claim 28, wherein controlling the heat emanating from the second die comprises reducing activity of the second die based on the leakage current of the first die.

30. The method, of claim 27, wherein the leakage sensor is a sensor configured to measure a voltage drop in the first die.

31. The method of claim 27, wherein the first die has a thermal tolerance, the thermal management unit is configured to control the temperature of the first die by controlling heat emanating from the second die based on the thermal tolerance of the first die.

32. The method of claim 31, wherein controlling the heat emanating from the second die based, on the thermal tolerance of the first die comprises determining the temperature of the first die based on the measured leakage current of the first die and comparing the measured temperature to the thermal tolerance of the first die.

33. The method of claim 27 further comprising positioning a heat reducing mechanism within the package, the heat reducing mechanism coupled to the thermal management unit.

34. The method, of claim 33, wherein the first die is a memory and the heat reducing mechanism is a memory controller.

35. The method of claim 33, wherein the heat reducing mechanism reduces heat by performing one of at least Dynamic Voltage and Frequency Scaling (DVFS), Dynamic Frequency Scaling (DFS), clock gating, and power collapsing.

36. The method, of claim 27, wherein the package is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

37. A semiconductor package comprising:

a first die comprising a plurality of through substrate vias (TSVs);

a second die coupled to the plurality of TSVs, the second die capable of heating the first die via the plurality of TSVs;

a sensor configured to measure a property of the first die; and

.

a thermal management unit coupled to the sensor, the thermal management unit configured to control a temperature of the first die based on the property of the first die.

38. The semiconductor package of claim 37, wherein the sensor is one of at least a temperature sensor and/or leakage current sensor.

39. The semiconductor package of claim 37, wherein the thermal management unit is configured to control the temperature of the first die by controlling heat emanating from the second die based on the property of the first die.

40. The semiconductor package of claim 37, wherein the first die, the second die and the thermal management unit are part of at least one of a System in Package (SiP) and System on Glass (SoG).

41. The semiconductor package of claim 37, wherein the package is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile phone, a smartphone, a personal digital assistant, a fixed, location terminal, a tablet computer, and/or a laptop computer.

42. A method for manufacturing a semiconductor package, the method comprising;

positioning a first die on a packaging substrate, the first die comprising a

plurality of through substrate vias (TSVs);

positioning a second die adjacent to the first die, the second die capable of heating the first die, the first die and the second die coupled to each other via the plurality of TSVs;

positioning a sensor within the package, the sensor configured to measure a property of the first die; and

positioning a thermal management unit within the package, the thermal management unit coupled to the sensor, the thermal management unit configured to control a temperature of the first die based on the property of the first die.

43. The method of claim 42, wherein the sensor is one of at least a temperature sensor and/or leakage current sensor,

44. A method, for managing temperature in a package comprising a first die and a second die, comprising:

measuring a property of a first die, the first die coupled to the second die via a plurality of through substrate vias (TSVs); and

controlling the temperature of the first die by reducing activity of the second die based on the measured property of the first die.

45. The method of claim 44, wherein the property of the first die is a temperature of the first die, the first die being a memory die.

46. The method of claim 44, wherein the property of the first die is a leakage current of the first die, the first die being a memory die.

47. A computer readable storage medium comprising one or more instructions for managing temperature in a semiconductor package comprising a first die and a second die, which when executed by at least one processor, causes the at least one processor to:

measure a property of a first die, the first die coupled to the second die via a plurality of through substrate vias (TSVs); and

control the temperature of the first die by reducing activity of the second die based on the measured property of the first die.

48. The computer readable storage medium of claim 47, wherein the property of the first die is a temperature of the first die, the first die being a memory die.

49. The computer readable storage medium of claim 47, wherein the property of the first die is a leakage current of the first die, the first die being a memory die.

50. A method, for managing temperature in a semiconductor package comprising a first die and a second die, comprising:

measuring a leakage current of a first die; and

controlling the temperature of the first die by reducing activity of the second die based on the leakage current of the first die.

51. The method of claim 50, wherein measuring the leakage current of the first die comprises measuring a voltage drop across the first die.

52. The method of claim 50, wherein reducing the activity of the second die reduces heat emanating from the second die.

53. A computer readable storage medium comprising one or more instructions for managing temperature in a semiconductor package comprising a first die and a second, die, which when executed by at least one processor, causes the at least one processor to:

measure a leakage current of a first die; and

control the temperature of the first die by reducing activity of the second die based on the leakage current of the first die.

54. The computer readable storage medium of claim 53, wherein the one or more instructions, which when executed by at least one processor, causes the at least one processor to measure the leakage current of the first die comprises one or more instructions, which when executed by at least one process, causes the at least one processor to measure a voltage drop across the first die,

55. The computer readable storage medium of claim 53, wherein the one or more instructions, which when executed by at least one processor, causes the at least one processor to reduce the activity of the second, die comprises one or more instructions, which when executed by at least one process, causes the at least one processor to reduces heat emanating from the second die.