ERROR DETECTION AT AN OSCILLATOR

• US 20140022022A1
• Filed: 07/17/2012
• Published: 01/23/2014
• Est. Priority Date: 07/17/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Choy, Jon S.
• Granted Patent: US 8,786,374 B2
• Time in Patent Office: Days
• US Class Current: 331/57
• CPC Class Codes: G01R 31/2824 testing of oscillators or resonators
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

An error detection system employs a chain of delay elements connected in an open loop configuration. To determine whether the oscillator is operating within a specified set of parameters, the error detection system applies a start pulse to an input of the open-loop chain of delay elements. The error detection system compares the resulting output signal with the output of the oscillator. If the oscillator has locked onto a harmonic of the intended output frequency, the comparison of the output signals will indicate an error.

Claims

1. A method, comprising:

generating an output signal at an open-loop chain of delay elements; and

determining an error at an oscillator based on the output signal.

2. The method of claim 1, wherein determining the error comprises determining the error based on a comparison between the output signal of the open-loop chain of delay elements and an output signal of the oscillator.

3. The method of claim 2, wherein determining the error comprises:

enabling a counter based on the output signal of the open-loop chain of delay elements;

asserting a signal to change a value stored at the counter based on the output signal of the oscillator; and

determining the error based on the value stored at the counter.

4. The method of claim 3, wherein enabling the counter comprises enabling the counter based on a logical combination of the output signal of the open-loop chain of delay elements and a start pulse.

5. The method of claim 4, wherein generating the output signal of the open-loop chain of delay elements comprises applying the start pulse to an input of the open-loop chain of delay elements to generate the output signal.

6. The method of claim 4, further comprising generating the start pulse at a control module synchronized with the output signal of the oscillator.

7. The method of claim 1, further comprising setting an indicator at a processor in response to determining the error.

8. The method of claim 1, further comprising resetting the oscillator in response to determining the error.

9. The method of claim 1, wherein the oscillator comprises a plurality of delay elements, the delay elements of the oscillator having a same circuit configuration as the delay elements of the open loop chain of delay elements.

10. A method, comprising:

enabling a counter based on an output signal of an open-loop chain of delay elements;

adjusting the counter based on an output of an oscillator;

detecting an error at the oscillator based on a value of the counter.

11. The method of claim 10, further comprising:

generating the output signal based upon a start pulse generated at a control module; and

synchronizing the control module based on the output of the oscillator.

12. The method of claim 11, wherein synchronizing the control module comprises generating a signal based on the output of the oscillator, the signal having a lower frequency than the output of the oscillator, and synchronizing the control module using the first signal.

13. The method of claim 12, wherein synchronizing the control module using the signal comprises synchronizing the control module using the first signal in response to determining an error in operation of the control module.

14. A device, comprising:

an oscillator;

an open-loop chain of delay elements; and

an error detection module to detect an error at an output signal of the oscillator based on the output signal of the oscillator and an output signal of the open-loop chain of delay elements.

15. The device of claim 14, wherein the error detection module determines the error based on a comparison between the output signal of the open-loop chain of delay elements and an output signal of the oscillator.

16. The device of claim 14, wherein the error detection module comprises a counter, the counter comprising:

an enable input coupled to an output of the open-loop chain of delay elements;

an adjustment input coupled to an output of the oscillator, the counter to adjust a stored value in response to assertion of a signal at the adjustment input when a signal at the enable input is asserted; and

wherein the error detection module is to determine the error based on the stored value.

17. The device of claim 16, wherein the error detection module further comprises a logic circuit to perform an AND function comprising an input to receive a start pulse, an input coupled to the output of the open-loop delay chain, and an output coupled to the enable input of the counter.

18. The device of claim 17, wherein the open-loop chain of delay elements comprises an input to receive the start pulse.

19. The device of claim 17, wherein the error detection module comprises a control module to generate the start pulse, the control module synchronized based on the output signal of the oscillator.

20. The device of claim 14, wherein the oscillator comprises a plurality of delay elements, the delay elements of the oscillator having a same circuit configuration as the delay elements of the open loop chain of delay elements.