CREATING UNIQUE IDENTIFICATION FOR AN ARRAY ELEMENT

• US 20140022834A1
• Filed: 11/03/2011
• Published: 01/23/2014
• Est. Priority Date: 11/03/2010
• Status: Abandoned Application

• Current Assignee: Anokiwave, Inc. (Qorvo, Inc.)
• Original Assignee: Anokiwave, Inc. (Qorvo, Inc.)
• Inventors: Jain, Nitin
• Application Number:
  US13/288,910
• Publication Number:
  US 20140022834A1
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: H01Q 21/0025 Modular arrays
• CPC Class Codes: H01Q 3/385 Scan control logics

Abstract

A circuit arrangement for assigning identification address to each element of an array of elements of a phased array, or assigning a unique digital word to a isolated circuit. In one embodiment two external resistors are used to provide an analog voltage. That voltage can be converted to digital word and stored in a chip using latches and registers. The stored digital word can then be use as address for the army element used in phased array. Thereby access to the array element can achieved using the address as a header of a digital bit stream.

Claims

1. A circuit comprising:

(a) a first circuit means that creates a unique analog signal

(b) a second circuit means that converts said unique analog signal to a unique digital word,

(c) a digitally controllable circuit having a plurality of possible states and an input digital port connected to receive said digital word, the state of said circuit being controllable by said digital input at said digital port,

second circuit being arranged to supply said unique digital word to said input digital port of said digitally controllable circuit,

whereby said digital controllable circuit can be assigned a unique state selected from said plurality of possible states.

2. The circuit of claim 1 wherein said digitally controllable component and said second circuit means are integrated in same package.

3. The circuit of claim 2 wherein said first circuit means is outside of said package.

4. The circuit of claim 3 wherein said package is an array element of a phased array.

5. The circuit of claim 2 wherein said digitally controllable component and said second circuit means are monolithic integrated circuits and said package is a plastic package.

6. The circuit of claim 1, further including a digital storage means for storing said unique digital word.

7. The circuit of claim 6 wherein said digital storage means is a register comprising a plurality of digital latches and flip-flops.

8. The circuit of claim 1 wherein said first circuit means comprises two resistors connected in series between a supply voltage and ground and forming a middle node, whereby said unique analog signal is generated from the voltage at said middle node of said resistors.

9. The circuit of claim 1 wherein said digitally controllable component has a digital buffer for storing digital address of said digitally controllable component, and a means for storing said unique digital word in said digital buffer, thereby assigning a unique address for said circuit.