METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A PATTERNED GATE DIELECTRIC AND STRUCTURE THEREFOR

• US 20140027813A1
• Filed: 07/24/2012
• Published: 01/30/2014
• Est. Priority Date: 07/24/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Kuruc, Marian, Vavro, Iuraj
• Granted Patent: US 8,946,002 B2
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.

Claims

1. A method of forming an insulated gate semiconductor device comprising the steps of:

providing a region of semiconductor material having a major surface;

forming a first trench extending from the major surface into the region of semiconductor material;

forming a first dielectric layer overlying surfaces of the first trench;

forming a photosenstive layer overlying the first dielectric layer, wherein the photosensitive layer is configured to protect at least a portion of the first dielectric layer along lower surfaces of the first trench;

removing at least a portion of the first dielectric layer from at least one upper sidewall surface of the first trench;

removing the photosensitive layer;

forming a second dielectric layer along the at least one upper sidewall surface, wherein the first and second dielectric layers have different thicknesses; and

forming a first conductive electrode along at least one of the first and second dielectric layers.

2. The method of claim 1, wherein forming the first conductive electrode comprises forming the first conductive electrode overlying surfaces of the first and second dielectric layer, and wherein the second dielectric layer is thinner than the first dielectric layer.

3. The method of claim 1, wherein forming the first conductive electrode comprises forming the first conductive electrode along surfaces of the first dielectric layer, the method further comprising the steps of:

forming a third dielectric layer overlying the first conductive electrode, and

forming a second conductive electrode along surfaces of the second dielectric layer, wherein the second conductive electrode is configured as a gate electrode, and wherein the first conductive electrode is configured as a shield electrode.

4. The method of claim 1, wherein removing at least a portion of the first dielectric layer from at least one upper sidewall surface of the first trench comprises removing a portion of the first dielectric layer from a first upper sidewall surface while leaving the first dielectric layer along a second upper sidewall surface of the first trench opposite to the first upper sidewall, and wherein forming the second dielectric layer comprises forming the second dielectric layer along the first upper sidewall surface.

5. The method of claim 1, wherein forming the first conductive electrode comprises forming a gate electrode, and wherein removing at least a portion of the first dielectric layer comprises removing portions of the first dielectric layer from opposing sidewall surfaces of the first trench.

6. The method of claim 1 further comprising:

forming a second trench extending from the major surface;

forming the first dielectric layer along surfaces of the second trench; and

forming the photosensitive layer along surfaces of the first dielectric layer within the second trench.

7. The method of claim 6, wherein removing at least a portion of the first dielectric layer from at least one upper sidewall surface of the first trench comprises removing at least a portion of the first dielectric layer from at least one upper sidewall surface of the first trench without removing the first dielectric layer from the second trench.

8. The method of claim 7 further comprising:

forming a second conductive electrode within the second trench;

forming a base region adjacent both the first and second trenches; and

forming an emitter region adjacent the first trench, but not the second trench.

9. The method claim 8 further comprising forming an emitter electrode coupled to the emitter region and the second conductive electrode.

10. The method of claim 1, wherein removing at least a portion of the first dielectric layer includes removing the first dielectric layer from both upper sidewall surfaces of the first trench, and wherein forming the second dielectric layer comprises forming the second dielectric layer along both upper sidewall surfaces of the first trench, and wherein the method further comprises:

forming first and second base regions adjacent opposites sides of the first trench;

forming an emitter region in the first base region, but not the second base region; and

forming a conductive contact to the emitter region and the first base region, but not the second base region.

11. The method of claim 1, wherein removing at least a portion of the first dielectric layer includes removing the first dielectric layer from only one sidewall surfaces of the first trench, and wherein forming the second dielectric layer comprises forming the second dielectric layer along the only one sidewall surface of the first trench, and wherein the method further comprises:

forming first and second base regions adjacent opposites sides of the first trench; and

forming an emitter region in the first base region adjacent the second dielectric layer, but not the second base region trench;

12. The method of claim 11 further comprising forming a conductive contact to the emitter region and the first base region, but not the second base region.

13. The method of claim 1, wherein forming the first dielectric layer comprises forming the first dielectric layer overlying the major surface, and wherein removing at least a portion of the first dielectric layer comprises removing at least a portion of the first dielectric layer overlying at least a portion of the major surface.

14. An insulated gate semiconductor device structure comprising:

a region of semiconductor material having a major surface;

a first trench extending from the major surface;

a second trench extending from the major surface and spaced apart from the first trench;

a first dielectric layer formed along lower surfaces of both the first and second trenches and at least a portion of a first upper surface of both the first and second trenches;

a second dielectric layer formed along at least a portion of a second upper surface of both the first and second trenches, wherein the second dielectric layer is thinner than the first dielectric layer;

a first conductive electrode formed within the first trench along the first and second dielectric layers; and

a second conductive electrode formed within the second trench along the first and second dielectric layers, wherein the first and second conductive electrodes and the second dielectric layer are configured to control a channel region within the region of semiconductor material.

15. The structure of claim 14, wherein the second upper surface is opposite to the first upper surface, and wherein the first upper surface has alternating portions comprising the first dielectric layer and the second dielectric layer, and wherein the device further comprises a first doped region formed adjacent the first trench and configured to form the channel.

16. The structure of claim 14 further comprising:

a third trench extending from the major surface between the first and second trenches;

the first dielectric layer formed along surfaces of third trench; and

a third electrode formed within the third trench.

18. A method for forming a semiconductor device comprising:

providing a region of semiconductor material having a major surface;

forming a first and second trenches extending from the major surface and spaced apart;

forming a first doped region within the region of semiconductor material;

forming a first layer along surfaces of the first and second trenches and along the major surface;

forming a photosensitive layer overlying the first layer;

forming openings in the photosensitive layer to expose the first layer along portions of upper sidewall surfaces of the first and second trenches and along portions of the major surface;

reducing the thickness of the exposed portions of the first layer, wherein other portions of the first layer remain along lower surfaces of the first and second trenches and the major surface;

forming a second layer where the first layer was reduced in thickness, wherein the second layer is thinner than the first layer; and

forming conductive electrodes in the first and second trenches along the first and second layers.

17. The structure of claim 18, wherein the third trench is formed absent the second dielectric layer, and wherein the third electrode is configured as a shield electrode.

19. The method of claim 18, wherein forming the openings includes forming a plurality of openings that are spaced apart along upper sidewall surfaces of the first and second trenches, and wherein at least one opening exposes adjoining portions of the upper sidewall of the first trench, the major surface, and the upper sidewall surface the second trench.

20. The method of claim 18, wherein forming the photosensitive layer includes forming a positive photoresist layer, and wherein forming the openings includes exposing portions of the positive photoresist layer to a light source through a mask and developing the exposed portions, and wherein forming the conductive electrode in first trench includes forming a gate electrode, and wherein forming the conductive electrode in the second trench includes forming a shield electrode.

21. A method for forming an insulated gate semiconductor device comprising:

forming a trench extending from a major surface of a region of semiconductor material;

forming a first dielectric layer along surfaces of the trench;

providing a patterned layer overlying the first dielectric layer including a plurality of laterally spaced apart openings along an upper surface of the trench;

reducing the thickness of the first dielectric layer through the openings while leaving other portions of the first dielectric layer in place along other surfaces of the trench adjacent the openings;

forming a second dielectric layer along those portions of the trench where the first dielectric layer was reduced in thickness;

forming a control electrode adjacent the first and second dielectric layers within the trench, wherein the second dielectric layer is configured as a gate dielectric layer and the first dielectric layer is thicker than the second dielectric layer.