Fluctuation Resistant FDSOI Transistor with Implanted Subchannel

• US 20140027854A1
• Filed: 07/25/2013
• Published: 01/30/2014
• Est. Priority Date: 07/28/2012
• Status: Active Grant

• Current Assignee: Semiwise Limited
• Original Assignee: Gold Standard Simulations Ltd (Synopsys Incorporated)
• Inventors: Asenov, Asen
• Granted Patent: US 9,190,485 B2
• Time in Patent Office: Days
• US Class Current: 257/348
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. A highly localized ion implantation is used to set the threshold voltage of the transistor and to improve the short channel behavior of the final device. Based on high-K metal gate technology, this transistor has reduced threshold uncertainty and superior source and drain conductance.

Claims

1. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising:

a semiconductor on insulator (SOI) substrate having a semiconductor layer on an insulator layer, which insulator layer is on an underlying substrate;

a source region and a drain region formed in the semiconductor layer;

a semiconductor channel region separating the source and the drain regions, the semiconductor channel region having a doping ranging from undoped to less than 10¹⁷ doping ions/cm³;

the semiconductor channel region having substantially vertical sides, with the source and drain regions each having an edge region truncated by the vertical sides of the semiconductor channel region;

the semiconductor channel region having a thickness of between 5 nm to 15 nm;

a doped layer under the semiconductor channel region having a doping that is greater than the doping of the semiconductor channel region and extending through the semiconductor layer to the insulator layer;

a gate dielectric over the semiconductor channel region; and

,

a conductive gate region over the gate dielectric.

2. The MOSFET of claim 1 wherein the source and drain regions extend through the semiconductor layer to the insulator layer.

3. The MOSFET of claim 1 wherein the doping in the doped layer under the semiconductor channel region is one of:

acceptors for an N-type MOSFET and donors for a P-type MOSFET.

4. The MOSFET of claim 1, wherein the doped layer under the semiconductor channel region is fully depleted at operational voltages of the MOSFET.

5. The MOSFET of claim 1, further comprising:

a pair of passive spacers above the semiconductor layer, each having substantially vertical faces spaced apart and defining a length of the conductive gate region.

6. The MOSFET of claim 5, wherein the semiconductor channel region fills an etched recess in the semiconductor layer between the spacers.

7. The MOSFET of claim 6 wherein the semiconductor channel region is an epitaxially grown semiconductor region in the etched recess.

8. The MOSFET of claim 1 wherein the gate dielectric is one or more dielectric layers having an effective dielectric constant greater than 6.

9. The MOSFET of claim 1 wherein the conductive gate region is a metal gate region.

10. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising:

a semiconductor on insulator (SOI) substrate having a silicon layer on an oxide layer, which oxide layer is on an underlying substrate;

a source region and a drain region extending through the semiconductor layer to the oxide layer;

an epitaxially grown semiconductor channel region truncating an edge of the source and the drain regions, the semiconductor channel region having a doping ranging from undoped to not to exceed 10¹⁷ doping ions/cm³;

the semiconductor channel region having substantially vertical sides, with the source and drain regions each having an edge region truncated by the vertical sides of the semiconductor channel region;

the semiconductor channel region having a thickness of between 5 nm to 15 nm and not extending through the semiconductor layer to the insulator layer;

a doped layer under the semiconductor channel region having a doping that is greater than the doping of the semiconductor channel region and extending through the semiconductor layer to the insulator layer;

a gate oxide over the semiconductor channel region; and

,

a metal gate region over the gate dielectric.

11. The MOSFET of claim 10 wherein the doping in the doped layer under the semiconductor channel is one of:

acceptors for an N-type MOSFET and donors for a P-type MOSFET.

12. The MOSFET of claim 10, wherein the doped layer under the semiconductor channel is fully depleted at operational voltages of the MOSFET.

13. The MOSFET of claim 10, further comprising a pair of passive spacers above the semiconductor layer, each having substantially vertical faces spaced apart and defining a length of the conductive gate region.

14. The MOSFET of claim 10, wherein the semiconductor channel region fills an etched recess in the semiconductor layer between the spacers.

15. A method of forming a MOSFET comprising:

providing an underlying substrate with a buried oxide layer thereon and a first semiconductor layer on the buried oxide layer;

forming a sacrificial gate structure above a region designated to be the transistor channel;

creating source and drain structures in the first semiconductor layer comprising source and drain extensions, sidewall spacers adjacent the sacrificial gate, and highly conductive source and drain regions contacting the source and drain extensions, respectively;

etching away the sacrificial gate structure;

implanting in the first semiconductor layer aligned with and below the sidewall spacers, a doped region adjacent and extending to the buried oxide layer;

epitaxially growing a semiconductor channel region in a recess in the first semiconductor layer over the doped region of a first doping level that extends to the buried oxide layer, the recess being formed by anisotropic processes using the gate spacers as a mask;

depositing a dielectric stack over the epitaxially grown semiconductor channel region; and

,

depositing a conductive gate over the dielectric stack;

wherein epitaxially growing a semiconductor channel region in the recess and all subsequent processes are low temperature processes not subjecting the MOSFET to temperatures exceeding 650°

C.

16. The method of claim 15 wherein forming in the first semiconductor layer aligned with and below the sidewall spacers, a doped region adjacent and extending to the buried oxide layer comprises forming the doped region by ion implantation using the sidewall spacers as a mask, and etching away part of the first semiconductor layer by an anisotropic process using the gate spacers as a mask.

17. The method of claim 16 wherein implanting of the doped region in the first semiconductor layer aligned with and below the sidewall spacers precedes the etching away part of the first semiconductor layer by an anisotropic process using the gate spacers as a mask.

18. The method of claim 16 wherein the implanting of the doped region by ion implantation using the sidewall spacers as a mask follows the etching away part of the first semiconductor layer by an anisotropic process using the gate spacers as a mask.

19. The method of claim 15 wherein etching away the sacrificial gate structure includes etching a recess in the first semiconductor layer using the sidewall spacers as a mask, the recess not extending to the buried oxide layer, and wherein the doped region adjacent and extending to the buried oxide layer is formed by implantation after the recess is formed.

20. The method of claim 15 wherein the source and drain regions extend through the first semiconductor layer to the buried oxide layer.

21. The method of claim 20 wherein the dielectric stack has an effective dielectric constant of at least 6.

22. The method of claim 15 further comprising depositing a conductive gate handle over the metal gate.

23. The method of claim 15 wherein the metal gate is formulated for specific work functions to set the threshold voltage of the MOSFET.

24. The method of claim 23 wherein the semiconductor channel region is germanium or silicon-germanium.

25. The method of claim 15 wherein the doping in the doped region adjacent and extending to the buried oxide layer is one of:

acceptors for an N-type MOSFET and donors for a P-type MOSFET.

26. The method of claim 15 wherein the doping in the semiconductor channel region is in the range of undoped to not exceeding 10¹⁷ doping ions/cm³.

27. The method of claim 15 wherein the semiconductor channel region is undoped.

28. The method of claim 15 wherein the first semiconductor layer and the semiconductor channel region are silicon.

29. A method of forming a MOSFET comprising:

providing an underlying substrate with a buried oxide layer thereon and a first semiconductor layer on the buried oxide layer;

providing a second oxide layer over the first semiconductor layer;

forming a sacrificial gate structure on the second oxide layer;

implanting through the second oxide layer a source extension on one side of the sacrificial gate structure and a drain extension on a second side of the sacrificial gate structure opposite the first side of the sacrificial gate structure;

depositing a first dielectric layer over the top of the second oxide layer and the sacrificial gate structure;

anisotropically etching the first dielectric layer to form gate sidewall spacers;

implanting, through the second oxide layer, source and drain regions which connect to the source and drain extensions;

removing the exposed regions of the second oxide layer;

depositing a second dielectric layer over the second oxide layer, the gate spacers and the sacrificial gate structure;

etching away the sacrificial gate structure;

implanting in the first semiconductor layer aligned with and below the sidewall spacers, a doped region adjacent and extending to the buried oxide layer;

epitaxially growing a semiconductor channel region in a recess in the first semiconductor layer over the doped region adjacent that extends to the buried oxide layer, the recess being formed by anisotropic processes using the gate spacers as a mask, the epitaxial channel region having a second doping level lower than the first doping level;

depositing a dielectric stack over the epitaxially grown semiconductor channel region; and

,

depositing a metal gate over the dielectric stack;

the epitaxially growing a semiconductor channel region in the recess over the second semiconductor layer and all succeeding steps being low temperature processes not subjecting the MOSFET to temperatures exceeding 650°

C.

30. The method of claim 29 wherein implanting of the doped region in the first semiconductor layer aligned with and below the sidewall spacers precedes the etching away part of the first semiconductor layer by an anisotropic process using the gate spacers as a mask.

31. The method of claim 29 wherein the implanting of the doped region by ion implantation using the sidewall spacers as a mask follows the etching away part of the first semiconductor layer by an anisotropic process using the gate spacers as a mask.