SELF-ALIGNED 3-D EPITAXIAL STRUCTURES FOR MOS DEVICE FABRICATION

• US 20140027860A1
• Filed: 07/27/2012
• Published: 01/30/2014
• Est. Priority Date: 07/27/2012
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Glass, Glenn A., Aubertine, Daniel B., Murthy, Anand S., Ghani, Tahir, Thareja, Gaurav
• Granted Patent: US 9,728,464 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility

Abstract

Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Claims

1. A method for forming a fin-based transistor structure, the method comprising:

forming a plurality of fins on a substrate, each fin extending from the substrate;

forming a shallow trench isolation on opposing sides of each fin;

recessing at least some of the fins to provide a first set of recesses; and

forming a substitute fin of a first type in each recess of the first set of recesses, each substitute fin of the first type comprising a channel of the transistor structure.

2. The method of claim 1 wherein recessing at least some of the fins to provide a first set of recesses comprises:

masking a first set of the fins of the plurality so as to leave a first set of unmasked sacrificial fins; and

recessing the first set of unmasked sacrificial fins to provide the first set of recesses.

3. The method of claim 2 further comprising:

planarizing each substitute fin of the first type, wherein said planarizing includes removing masking material over the first set of fins.

4. The method of claim 3 further comprising:

masking each of the substitute fins of the first type so as to leave a second set of unmasked sacrificial fins;

recessing the second set of unmasked sacrificial fins to provide a second set of recesses; and

forming a substitute fin of a second type in each recess of the second set of recesses.

5. The method of claim 4 wherein at least one common plane taken along a single axis cuts through respective channels of at least one substitute fin of the first type and at least one substitute fin of the second type.

6. The method of claim 4 wherein there is no common plane taken along a single axis that cuts through respective channels of the first and second type substitute fins.

7. The method of claim 4 wherein the substitute fins of the first type are configured differently than the substitute fins of the second type with respect to at least one of polarity, strain, and/or composition.

8. The method of claim 7 wherein the substitute fins of the first type are configured for one of PMOS or NMOS and the substitute fins of the second type are configured for the other of PMOS or NMOS.

9. The method of claim 4 further comprising:

planarizing each substitute fin of the second type, wherein said planarizing includes removing masking material over the substitute fins of the first type.

10. The method of claim 1 wherein recessing at least some of the fins to provide a first set of recesses comprises recessing all fins in the plurality.

11. The method of claim 1 further comprising:

recessing shallow trench isolation on the substrate to expose sidewalls of the substitute fins of the first type;

forming a gate over the substitute fins of the first type; and

forming source/drain regions associated with the gate.

12. The method of claim 1 wherein remaining fins of the plurality are not substitute fins and are of a second type, each remaining fin of the second type comprising a channel of the transistor structure.

13. The method of claim 12 further comprising:

recessing shallow trench isolation on the substrate to expose sidewalls of the substitute fins of the first type and the remaining fins of the second type; and

forming a gate structure over the substitute fins of the first type and the remaining fins of the second type; and

forming source/drain regions associated with the gate structure.

14. An integrated circuit formed by the method of claim 1.

15. A transistor device, comprising:

a first plurality of substitute fins of a first type on a substrate, each substitute fin of the first plurality extending from the substrate and comprising a channel area; and

a second plurality of other fins on the substrate, each fin of the second plurality extending from the substrate and comprising a channel area.

16. The device of claim 15 wherein the second plurality of other fins are also substitute fins of the first type.

17. The device of claim 15 wherein the second plurality of other fins are of a second type, and the channel areas of the first type substitute fins are configured differently than the channel areas of the second type other fins with respect to at least one of polarity, strain, and/or composition.

18. The device of claim 17 wherein the second type other fins are also substitute fins.

19. The device of claim 17 wherein the second type other fins are not substitute fins.

20. The device of claim 15 further comprising:

a shallow trench isolation on opposing sides of each fin of the first and second plurality of fins.

21. The device of claim 15 wherein at least one common plane taken along a single axis cuts through respective channel areas of at least one first type substitute fin and at least one of the other fins.

22. The device of claim 15 wherein there is no common plane taken along a single axis that cuts through respective channel areas of both any one of the first type substitute fins and any one of the other fins.

23. The device of claim 15 wherein the channel areas of the first type substitute fin are configured for one of PMOS or NMOS and the channel areas of the other fins are configured for the other of PMOS or NMOS.

24. The device of claim 15 further comprising:

a gate stack; and

source/drain regions.

25. An integrated circuit comprising the device of claim 15.

26. A system comprising the integrated circuit of claim 25.

27. A transistor device, comprising:

a first plurality of substitute fins of a first type on a substrate, each substitute fin of the first plurality extending from the substrate and comprising a channel area;

a second plurality of other fins on the substrate, each fin of the second plurality extending from the substrate and comprising a channel area;

a shallow trench isolation on opposing sides of each fin of the first and second plurality of fins;

a gate stack on multiple channel area surfaces of the first and second plurality of fins extending above the shallow trench isolation so as to provide multi-gates per fin; and

source/drain regions corresponding to at least one of the gates;

wherein at least one common plane taken along a single axis cuts through respective channel areas of at least one first type substitute fin and at least one of the other fins.

28. The device of claim 27 wherein the second plurality of other fins are of a second type, and the channel areas of the first type substitute fins are configured differently than the channel areas of the second type other fins with respect to at least one of polarity, strain, and/or composition.

29. The device of claim 27 wherein the other fins are also substitute fins that are compositionally different from the first type substitute fins.

30. The device of claim 29 wherein the channel areas of the first type substitute fin are configured for one of PMOS or NMOS and the channel areas of the other fins are configured for the other of PMOS or NMOS.