Reconfigurable and Auto-Reconfigurable Resonant Clock

• US 20140028407A1
• Filed: 07/26/2012
• Published: 01/30/2014
• Est. Priority Date: 07/26/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chern, Chan-Hong, Chung, Tao Wen, Lin, Chih-Chang, Huang, Ming-Chieh, Hsueh, Fu-Lung, Huang, Tsung-Ching
• Granted Patent: US 8,847,652 B2
• Time in Patent Office: Days
• US Class Current: 331/117.R
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03B 5/12 active element in amplifier being semiconductor device H03B5/14 takes precedence
• CPC Class Codes: H03B 5/32 being a piezoelectric resonator selection of piezoelectric material H10N30/00
• CPC Class Codes: H03K 5/15 Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors distributing, switching or gating arrangements H03K17/00

Abstract

The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.

Claims

1. A resonant clock system comprising:

a driver component configured to generate a driven input signal;

a clock load capacitor configured to receive the driven input signal; and

an inductor array configured to have an effective inductance according to a selected frequency and to generate a resonant clock output signal at the selected frequency.

2. The system of claim 1, wherein the selected frequency is one of a plurality of available frequencies.

3. The system of claim 2, wherein the effective inductance is one of a plurality of available effective inductances.

4. The system of claim 1, wherein the driver component includes a plurality of drivers of varied sizes and the driver component is configured to utilize one of the plurality of drivers according to the selected frequency.

5. The system of claim 1, wherein the driver component is configured to receive a phase locked loop (PLL) signal as an input signal.

6. The system of claim 1, wherein the effective inductance has an inductive reactance equal to a capacitive reactance of the clock capacitor at the selected frequency.

7. The system of claim 1, further comprising a configuration controller configured to provide inductor configuration information to the inductor array, the inductor configuration information corresponding to the selected frequency.

8. The system of claim 7, wherein the configuration controller is configured to provide driver configuration information to the driver component, the driver configuration information corresponding to the selected frequency.

9. The system of claim 1, further comprising a configuration controller configured to provide inductor configuration information to the inductor array, the inductor configuration information corresponding to a new selected frequency.

10. The system of claim 1, wherein the inductor array includes a plurality of high Q factor inductors.

11. The system of claim 10, wherein the inductor array further includes switches coupled to the high Q factor inductors, the switched configured to operate according to inductor configuration information.

12. The system of claim 10, wherein the plurality of high Q factor inductors are connected in series.

13. The system of claim 10, wherein the plurality of high Q factor inductors are connected in parallel.

14. The system of claim 1, further comprising an inductor configuration component configured to automatically generate and provide inductor configuration information to the inductor array, the inductor configuration information generated according to the resonant signal and a PLL signal.

15. The system of claim 14, wherein the inductor configuration component includes a frequency comparator configured to receive the PLL signal and the resonant signal and a state machine configured to generate the inductor configuration information according to an output signal of the frequency comparator.

16. A resonant clock system comprising:

a PLL configured to generate a PLL signal;

a driver component configured to receive the PLL signal and to provide a driven signal;

an inductor array of high Q factor inductors configured to receive the driven signal and to provide a resonant signal, wherein the inductor array has a plurality of selectable high Q factor inductance values; and

an inductor configuration component configured to provide inductor configuration information to the inductor array according to the PLL signal and the clock load.

17. The system of claim 16, wherein the inductor configuration component includes a frequency detector to detect frequencies of the PLL signal and the resonant signal.

18. The system of claim 16, wherein the inductor configuration component includes a PLL counter and a resonant signal counter, wherein the PLL counter counts cycles of the PLL signal and the resonant signal counter counts cycles of the resonant signal in a selected time interval.

19. A method of operating a resonant clock circuit having an inductor array, the method comprising:

providing the resonant clock circuit having the inductor array;

selecting a frequency of a plurality of available frequencies;

selecting an inductance value of a plurality of available inductance values according to the selected frequency;

configuring the inductor array according to the selected inductance value; and

generating a resonant clock signal using the configured inductor array and at the selected frequency.

20. The method of claim 19, wherein the selected inductance value is provided with a high Q factor.