METHOD OF ACCESSING A NON-VOLATILE MEMORY

• US 20140032813A1
• Filed: 07/24/2012
• Published: 01/30/2014
• Est. Priority Date: 07/24/2012
• Status: Active Grant

• Current Assignee: YEESTOR Microelectronics Co., Ltd.
• Original Assignee: Skymedi Corporation
• Inventors: Liu, Yi Chun, LEE, Chung-hsun, CHOU, Ming Hung
• Granted Patent: US 8,867,272 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/186 Passive fault masking when reading multiple copies of the same data
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A method of accessing a non-volatile memory is disclosed. Original bits of data are duplicated on a bit level to generate a plurality of duplicated bits corresponding to each original bit. At least one shielding bit is provided between the duplicated bits corresponding to different original bits. The duplicated bits and the at least one shielding bit are programmed to the non-volatile memory. The original bits are generated or determined according to the duplicated bits.

Claims

1. A method of accessing a non-volatile memory, comprising:

duplicating original bits of data on a bit level to generate a plurality of duplicated bits corresponding to each said original bit;

providing at least one shielding bit between the plurality of duplicated bits corresponding to different original bits;

programming the duplicated bits and the at least one shielding bit to the non-volatile memory; and

generating the original bits of data from the duplicated bits.

2. The method of claim 1, wherein the non-volatile memory comprises a flash memory.

3. The method of claim 1, wherein the data comprise protected data and at least one protecting code that is used for error detection and/or correction to ensure integrity of the protected data.

4. The method of claim 1, wherein the at least one shielding bit is programmed with data that is represented by a lowest voltage level.

5. The method of claim 1, wherein the duplicated bits corresponding to each said original bit are followed with at least one shielding bit that acts as the shielding.

6. The method of claim 1, wherein the shielding bit is programmed with dummy data.

7. The method of claim 1, wherein the duplicated bits corresponding to each said original bit are programmed to non-continuous first bit lines of a word line and to non-continuous second bit lines of the word line, the first bit lines being interspersed with the second bit lines such that the duplicated bits of the second bit lines act as the shielding bits.

8. The method of claim 7, wherein the first bit lines are even-numbered bit lines, and the second bit are odd-numbered bit lines.

9. The method of claim 1, wherein the duplicated bits corresponding to each said original bit are programmed to non-continuous first bit lines of a word line and dummy data are programmed to non-continuous second bit lines of the word line, the first bit lines being interspersed with the second bit lines such that the dummy data of the second bit lines act as the shielding bits.

10. The method of claim 1, wherein the duplicated bits corresponding to each said original bit are programmed to non-continuous first bit lines of a first word line and to non-continuous second bit lines of an adjacent second word line, and dummy data are programmed to non-continuous second bit lines of the first word line and to non-continuous first bit lines of the second word line, the first bit lines being interspersed with the second bit lines such that the dummy data of the second bit lines act as the shielding bits.

11. The method of claim 10, further comprising:

programming non-continuous first bit lines of a third word line with inverted duplicated bits that are inverted from the duplicated bits; and

programming non-continuous second bit lines of the third word line with dummy data.

12. The method of claim 1, wherein the duplicated bits and the shielding bits are programmed to a first word line, and dummy data are programmed to an adjacent second word line.

13. The method of claim 12, further comprising:

programming inverted duplicated bits that are inverted from the duplicated bits to a third word line; and

programming dummy data to a fourth word line that is adjacent to the third word line.

14. The method of claim 1, wherein the non-volatile memory comprises a multi-bit per cell memory.

15. The method of claim 14, wherein the duplicated bits and the shielding bits are programmed to all pages of a word line.

16. The method of claim 14, wherein the duplicated bits are programmed to a least significant bit (LSB) page of a word line, and dummy data are programmed to other pages of the word line.

17. The method of claim 14, wherein the multi-bit per cell memory is configured as a single-bit per cell memory, which is then programmed with the duplicated bits.

18. The method of claim 14, wherein only a least significant bit (LSB) page of a word line is programmed.

19. The method of claim 1, wherein the generating step comprises:

balloting the programmed duplicated bits corresponding to one said original bit, according to which majority of the programmed duplicated bits is determined as the original bit.

20. The method of claim 1, wherein the generating step comprises;

selecting one bit of the programmed duplicated bits corresponding to different original bits;

merging selected bits of the original bits of data; and

verifying the merged bits.

21. The method of claim 1, further comprising:

while programming to a first word line, allocating the duplicated bits corresponding to the original bit until a bad column is not encountered;

while programming to a second word line, allocating the duplicated bits corresponding to the original bit if a bad column is encountered, programming inverted duplicated bits that are inverted from the duplicated bits if the bad column is not encountered.

22. The method of claim 21, the duplicated bits and the inverted duplicated bits are respectively followed, with the at least one shielding bit.

23. The method of claim 21, in the generating step, further comprising:

reading the first word line and the second word line; and

comparing the data read from the first word line and the data read from the second word line to check presence of a bad column.

24. The method of claim 23, wherein the comparing step is performed on the read duplicated bit and the read inverted duplicated bit by a bit-wise logical exclusive-OR (XOR) operation.

25. The method of claim 23, wherein the generating step further comprises:

discarding the duplicated bits corresponding to the original bit in the first word line if the duplicated bits encounter the bad column.