Energy Conservation in a Multicore Chip

• US 20140032829A1
• Filed: 07/26/2012
• Published: 01/30/2014
• Est. Priority Date: 07/26/2012
• Status: Active Grant

• Current Assignee: Mercury Kingdom Assets Limited
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Solihin, Yan
• Granted Patent: US 9,275,696 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/403 Error protection encoding, e.g. using parity or ECC codes
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Technologies are described herein for conserving energy in a multicore chip via selectively refreshing memory directory entries. Some described examples may refresh a dynamic random access memory (DRAM) that stores a cache coherence directory of a multicore chip. More particularly, a directory entry may be accessed in the cache coherence directory stored in the DRAM. Some further examples may identify a cache coherence state of a block associated with the directory entry. In some examples, refresh of the directory entry stored in the DRAM may be selectively disabled based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.

Claims

1. A method for refreshing a dynamic random access memory (DRAM) that stores a cache coherence directory of a multicore chip, the method comprising:

accessing a directory entry in the cache coherence directory stored in the DRAM;

identifying a cache coherence state of a block associated with the directory entry; and

selectively disabling a refresh of the directory entry in the cache coherence directory stored in the DRAM based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.

2. The method of claim 1, wherein selectively disabling further comprises disabling the refresh of the directory entry when the cache coherence state is identified as one of an exclusive state, a modified state, an invalid state, or an uncached state.

3. The method of claim 1, the method further comprising selectively enabling the refresh of the directory entry when the cache coherence state is identified as one of an exclusive state, a modified state, an invalid state, or an uncached state.

4. The method of claim 1, the method further comprising selectively enabling the refresh of the directory entry when the cache coherence state is identified as a shared state.

5. The method of claim 1, the method further comprising:

when the cache coherence state of the block is identified as a shared state;

identifying a last time when the block was accessed;

calculating a difference between a current time and the last time;

determining if the difference exceeds a threshold;

disabling refresh of the directory entry when the difference exceeds the threshold; and

enabling refresh of the directory entry when the difference does not exceed the threshold.

6. The method of claim 1, wherein accessing the directory entry in the cache coherence directory stored in the DRAM comprises:

accessing the directory entry comprising a tag identifying the block, the cache coherence state of the block, a sharers item identifying which of a plurality of cache memories in the multicore chip store the block, and an error correction code (ECC) for detecting and/or correcting an error in the sharers item.

7. The method of claim 6, the method further comprising:

detecting an error in the sharers item based on the ECC associated with the block;

determining whether the detected error is correctable using the ECC; and

correcting the detected error using the ECC when the detected error is correctable.

8. The method of claim 7, the method further comprising:

when the detected error is not correctable using the ECC;

broadcasting a message to each cache memory of the plurality of cache memories in the multicore chip, wherein the message requests each cache memory to determine if the corresponding cache memory contains the block;

receiving replies to the message from each of the plurality of cache memories, and

updating the sharers item to correct the detected error based on the received replies.

9. The method of claim 7, wherein detecting the error in the sharers item based on the ECC comprises:

reading the sharers item and the ECC in the directory entry;

computing a new ECC based on the sharers item; and

detecting the error in the sharers item when the new ECC does not match the ECC in the directory entry.

10. The method of claim 6, wherein accessing the directory entry comprising the sharers item identifying which of the plurality of cache memories in the multicore chip store the block comprises:

accessing the sharers item comprising a bit vector, the bit vector comprising a plurality of bits, wherein each of the plurality of bits in the bit vector is associated with one or more cache memories of the plurality of cache memories in the multicore chip.

11. The method of claim 10, wherein detecting the error in the sharers item when the new ECC does not match the ECC in the directory entry comprises:

detecting up to a two-bit error in the bit vector and correcting a one-bit error in the bit vector using the ECC, the ECC comprising a 1-error-correction, 2-error-detection (1EC2ED) code.

12. The method of claim 11, further comprising:

detecting a greater than two-bit error in the bit vector using an additional error direction code contained in the directory entry.

13. A computer-readable storage medium having computer-executable instructions stored thereon which, when executed by a computing device, cause the computing device to:

access a directory entry in a cache coherence directory of a multicore chip stored in a dynamic random access memory (DRAM);

identify a cache coherence state of a block associated with the directory entry; and

selectively disable a refresh of the directory entry in the cache coherence directory stored in the DRAM based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.

14. The computer-readable storage medium of claim 13 having computer-executable instructions stored thereon which, when executed by the computing device, cause the computing device to:

selectively disable the refresh of the directory entry stored in the DRAM when the cache coherence state of the block is identified as one of an exclusive state, a modified state, an invalid state, or an uncached state.

15. The computer-readable storage medium of claim 13 having further computer-executable instructions stored thereon which, when executed by the computing device, cause the computing device to:

selectively enable the refresh of the directory entry stored in the DRAM when the cache coherence state of the block is identified as one of an exclusive state, a modified state, an invalid state, or an uncached state.

16. The computer-readable storage medium of claim 13 having further computer-executable instructions stored thereon which, when executed by the computing device, cause the computing device to:

selectively enable the refresh of the directory entry stored in the DRAM when the cache coherence state is identified as a shared state.

17. The computer-readable storage medium of claim 13 having further computer-executable instructions stored thereon which, when executed by the computing device, cause the computing device to:

when the cache coherence state of the block is identified as a shared state;

identify a last time when the block was last accessed;

calculate a difference between a current time and the last time;

determine if the difference exceeds a threshold;

disable the refresh of the directory entry stored in the DRAM when the difference is determined to exceed the threshold; and

enable the refresh of the directory entry stored in the DRAM when the difference is determined not to exceed the threshold.

18. The computer-readable storage medium of claim 13, wherein to refresh the directory entry, further causes the computing device to:

charge one or more capacitors corresponding to the directory entry.

19-25. -25. (canceled)

26. A multicore chip, comprising:

a plurality of processor cores and a plurality of cache memories, wherein each cache memory of the plurality of cache memories corresponds to one or more of the plurality of processor cores;

a directory stored in dynamic random access memory (DRAM), wherein the directory comprises a directory entry; and

a directory controller configured to;

access the directory entry in the directory;

identify the cache coherence state of a block associated with the directory entry; and

selectively disable a refresh of the directory entry in the directory based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.

27. The multicore chip of claim 26, wherein in being configured to selectively disable, the directory controller is configured to selectively disable the refresh of the directory entry when the cache coherence state of the block is identified as one of an exclusive state, a modified state, an invalid state, or an uncached state.

28. The multicore chip of claim 26, wherein the directory controller is further configured to:

selectively enable the refresh of the directory entry when the cache coherence state of the block is identified as one of an exclusive state, a modified state, an invalid state, or an uncached state.

29. The multicore chip of claim 26, wherein the directory controller is further configured to:

selectively enable the refresh of the directory entry when the cache coherence state is identified as a shared state.

30. The multicore chip of claim 26, wherein the directory controller is further configured to:

when the cache coherence state of the block is identified as a shared state;

identify a last time when the block was last accessed;

calculate a difference between a current time and the last time;

determine if the difference exceeds a threshold;

disable the refresh of the directory entry when the difference is determined to exceed the threshold; and

enable the refresh of the directory entry when the difference is determined not to exceed the threshold.

31. The multicore chip of claim 26, wherein to refresh the directory entry, the directory controller is further configured to:

charge of one or more capacitors corresponding to the directory entry.

32-38. -38. (canceled)