Energy Conservation in a Multicore Chip
First Claim
1. A method for refreshing a dynamic random access memory (DRAM) that stores a cache coherence directory of a multicore chip, the method comprising:
- accessing a directory entry in the cache coherence directory stored in the DRAM;
identifying a cache coherence state of a block associated with the directory entry; and
selectively disabling a refresh of the directory entry in the cache coherence directory stored in the DRAM based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.
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Accused Products
Abstract
Technologies are described herein for conserving energy in a multicore chip via selectively refreshing memory directory entries. Some described examples may refresh a dynamic random access memory (DRAM) that stores a cache coherence directory of a multicore chip. More particularly, a directory entry may be accessed in the cache coherence directory stored in the DRAM. Some further examples may identify a cache coherence state of a block associated with the directory entry. In some examples, refresh of the directory entry stored in the DRAM may be selectively disabled based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.
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Citations
32 Claims
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1. A method for refreshing a dynamic random access memory (DRAM) that stores a cache coherence directory of a multicore chip, the method comprising:
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accessing a directory entry in the cache coherence directory stored in the DRAM; identifying a cache coherence state of a block associated with the directory entry; and selectively disabling a refresh of the directory entry in the cache coherence directory stored in the DRAM based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A computer-readable storage medium having computer-executable instructions stored thereon which, when executed by a computing device, cause the computing device to:
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access a directory entry in a cache coherence directory of a multicore chip stored in a dynamic random access memory (DRAM); identify a cache coherence state of a block associated with the directory entry; and selectively disable a refresh of the directory entry in the cache coherence directory stored in the DRAM based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved. - View Dependent Claims (14, 15, 16, 17, 18)
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19-25. -25. (canceled)
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26. A multicore chip, comprising:
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a plurality of processor cores and a plurality of cache memories, wherein each cache memory of the plurality of cache memories corresponds to one or more of the plurality of processor cores; a directory stored in dynamic random access memory (DRAM), wherein the directory comprises a directory entry; and a directory controller configured to; access the directory entry in the directory; identify the cache coherence state of a block associated with the directory entry; and selectively disable a refresh of the directory entry in the directory based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved. - View Dependent Claims (27, 28, 29, 30, 31)
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32-38. -38. (canceled)
Specification