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Energy Conservation in a Multicore Chip

  • US 20140032829A1
  • Filed: 07/26/2012
  • Published: 01/30/2014
  • Est. Priority Date: 07/26/2012
  • Status: Active Grant
First Claim
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1. A method for refreshing a dynamic random access memory (DRAM) that stores a cache coherence directory of a multicore chip, the method comprising:

  • accessing a directory entry in the cache coherence directory stored in the DRAM;

    identifying a cache coherence state of a block associated with the directory entry; and

    selectively disabling a refresh of the directory entry in the cache coherence directory stored in the DRAM based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.

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