TRACKING MECHANISM FOR WRITING TO A MEMORY CELL
First Claim
Patent Images
1. A circuit comprising:
- a clock signal line configured to have a clock signal thereon;
a write driver;
a data circuit;
a memory cell;
a tracking write buffer;
a tracking write driver; and
a tracking cell,wherein the circuit is configured so that during a write operation of the memory cell based on the clock signalthe write driver circuit is configured to generate a write control signal on a write control line to control the memory cell;
the data circuit is configured to provide write data to the memory cell on a write data line;
the tracking write buffer is configured to generate a tracking write control signal on a tracking write control line to control the tracking cell;
the tracking write driver is configured to generate a tracking write data signal on a tracking write data line to be transferred to the tracking cell;
the data to be transferred to the tracking cell is transferred to the tracking cell based on a slower signal of the tracking write control signal and the tracking write data signal; and
the tracking cell is configured to generate a tracking signal based on the data transferred to the tracking cell.
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Abstract
A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.
91 Citations
20 Claims
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1. A circuit comprising:
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a clock signal line configured to have a clock signal thereon; a write driver; a data circuit; a memory cell; a tracking write buffer; a tracking write driver; and a tracking cell, wherein the circuit is configured so that during a write operation of the memory cell based on the clock signal the write driver circuit is configured to generate a write control signal on a write control line to control the memory cell; the data circuit is configured to provide write data to the memory cell on a write data line; the tracking write buffer is configured to generate a tracking write control signal on a tracking write control line to control the tracking cell; the tracking write driver is configured to generate a tracking write data signal on a tracking write data line to be transferred to the tracking cell; the data to be transferred to the tracking cell is transferred to the tracking cell based on a slower signal of the tracking write control signal and the tracking write data signal; and the tracking cell is configured to generate a tracking signal based on the data transferred to the tracking cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of writing to a memory cell comprising:
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based on a clock signal, generating a first edge of a write control signal on a write control line of the memory cell; generating a first edge of a write data signal on a write data line of the memory cell; generating a first edge of a tracking write control signal on a tracking write control line; and generating a first edge of a tracking write data signal on a tracking write data line; based on a slower signal of the tracking write control signal and the tracking write data signal, generating a reset signal; and based on the reset signal, generating a second edge of the write control signal; and generating a second edge of the write data signal, wherein a time delay of the tracking write control signal is greater than a time delay of the write control signal; and a time delay of the tracking write data signal is greater than a time delay of the write data signal. - View Dependent Claims (10, 11, 12, 13)
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14. A tracking circuit in a memory macro comprising:
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a clock generator circuit; a tracking cell; a tracking write buffer; a first plurality of memory cells; a tracking write control line coupled with the tracking cell, the tracking write buffer, and the first plurality of memory cells; a tracking write driver; a second plurality of memory cells; and a tracking write data line coupled with the tracking cell, the tracking write driver, and the second plurality of memory cells, wherein the clock generator circuit is configured to receive a first clock signal from outside of the memory macro, and, based on the first clock signal, generate a first edge of a second clock signal; the tracking write buffer, based on the first edge of the second clock signal, is configured to generate a first edge of a tracking write control signal on the tracking write control line; the tracking write driver, based on the first edge of the second clock signal, is configured to generate a first edge of a tracking write data signal on the tracking write data line; and the tracking cell is configured to be written with data represented by the tracking write data signal based on a slower signal of the tracking write control signal and the tracking write data signal. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification