Post-silicon validation using a partial reference model

• US 20140032969A1
• Filed: 07/29/2012
• Published: 01/30/2014
• Est. Priority Date: 07/29/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Landa, Shimon, Nahir, Amir
• Granted Patent: US 8,990,622 B2
• Time in Patent Office: Days
• US Class Current: 714/33
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

Method, system and product for post silicon validation using a partial reference model. The method performed by a device having registers, the method comprising: first executing, by the device when operating in trace mode, a test-case, wherein during the execution utilizing a partial reference model to determine an expected value of at least one register; second executing, by the device when operating in non-trace mode, the test-case; and in response to said second executing, checking values of registers based on, at least in part, values determined during said first execution.

Claims

1. A computer-implemented method, the method performed by a device, wherein the device having registers, the method comprising:

first executing, by the device when operating in trace mode, a test-case, wherein during the execution utilizing a partial reference model to determine an expected value of at least one register;

second executing, by the device when operating in non-trace mode, the test-case; and

in response to said second executing, checking values of registers based on, at least in part, values determined during said first execution.

2. The computer-implemented method of claim 1, wherein the partial reference model is a reference model providing expected values for a strict subset of all possible inputs to an instruction.

3. The computer-implemented method of claim 1, wherein said checking is performed based on the partial reference model and without intrusively interfering with the execution of the test-case

4. The computer-implemented method of claim 1, further comprises generating the test-case.

5. The computer-implemented method of claim 4, wherein said generating comprises:

determining an instruction to be generated having a set of input registers and a target register;

determining a combination of values to the input registers for which the partial reference model provides an expected result; and

generating the test-case including the instruction, wherein the test-case is configured to initialize the input registers with the combination of values.

6. The computer-implemented method of claim 1, wherein said second executing the test-case and checking are preformed repeatedly with respect to the test-case to check for consistency.

7. The computer-implemented method of claim 1, wherein said first executing the test-case, said second executing the test-case and said checking are performed based on instructions in a post-silicon testing program which is retained by a memory of the device, wherein the post-silicon testing program comprising the partial reference model.

8. The computer-implemented method of claim 7, wherein the partial reference model is derived from a full reference model in order to be comprised by the post-silicon testing program.

9. The computer-implemented method of claim 1, wherein said first executing comprises:

monitoring values of the registers after execution of each instruction of the test-case;

determining the expected value of the at least one register after performing an instruction of the test-case based on the partial reference model; and

verifying that the value of the at least one register is not overwritten after the instruction is executed and before test-case ends.

10. The computer-implemented method of claim 1, wherein the trace mode is an intrusive mode of operation in which in response to an instruction of the test-case being performed the device interrupts the execution and allows for execution of instructions that are not comprised by the test-case.

11. The computer-implemented method of claim 1, wherein the partial reference model is a reference model relating to instructions selected from the group consisting of:

floating point instructions, encryption instructions and compression instructions.

12. A computer program product embedded a non-transitory computer readable medium,

wherein said computer program product is a post-silicon testing program of a device;

wherein said non-transitory computer readable medium retaining a partial reference model of the device; and

wherein said non-transitory computer readable medium retaining instructions for the device, which instructions when read by the device, cause the device to utilize the partial reference model when executing a reference pass of a test-case.

13. The computer program product of claim 12 wherein the instructions, when read by the device, cause the device to utilize the partial reference model when generating the test-case.

14. A computer program product comprising:

a non-transitory computer readable medium retaining program instructions, which instructions when read by a device, cause the device to perform the steps of;

first executing, by the device when operating in trace mode, a test-case, wherein during the execution utilizing a partial reference model to determine an expected value of at least one register;

second executing, by the device when operating in non-trace mode, the test-case; and

in response to said second executing, checking values of registers based on, at least in part, values determined during said first execution.