MEMORY CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM, AND MEMORY CONTROL METHOD
First Claim
1. A memory system comprising:
- a non-volatile semiconductor memory that includes memory cells each storing 3 bits, and each bit data of the 3 bits data is allocated to each threshold value distribution;
a control unit that performs control such that the threshold value distribution is allocated by first data coding in which a first page, a second page, and a third page are each 1 bit and data is written to the non-volatile semiconductor memory, a first bit of the 3 bits data indicating data of the first page, a second bit thereof indicating data of the second page, and a third bit thereof indicating data of the third page; and
an encoding unit that generates a first parity with a first size for user data stored in the first page, generates a second parity with a second size for user data stored in the second page, and generates a third parity with a third size for user data stored in the third page,wherein the control unit performs control such that the user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by the first data coding and performs control such that a portion of the second parity and a portion of the third parity are allocated to each threshold value by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit and are written to the non-volatile semiconductor memory.
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Accused Products
Abstract
According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes memory cells each storing 3 bits, a control unit that writes data to the non-volatile semiconductor memory, and an encoding unit that generates a first parity for user data stored in the first page, a second parity for user data stored in the second page, and a third parity for user data stored in the third page. The user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by a first data coding and a portion of the second parity and a portion of the third parity are written to the non-volatile semiconductor memory by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit.
50 Citations
13 Claims
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1. A memory system comprising:
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a non-volatile semiconductor memory that includes memory cells each storing 3 bits, and each bit data of the 3 bits data is allocated to each threshold value distribution; a control unit that performs control such that the threshold value distribution is allocated by first data coding in which a first page, a second page, and a third page are each 1 bit and data is written to the non-volatile semiconductor memory, a first bit of the 3 bits data indicating data of the first page, a second bit thereof indicating data of the second page, and a third bit thereof indicating data of the third page; and an encoding unit that generates a first parity with a first size for user data stored in the first page, generates a second parity with a second size for user data stored in the second page, and generates a third parity with a third size for user data stored in the third page, wherein the control unit performs control such that the user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by the first data coding and performs control such that a portion of the second parity and a portion of the third parity are allocated to each threshold value by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit and are written to the non-volatile semiconductor memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory controller that controls a non-volatile semiconductor memory which includes memory cells each storing 3 bits, and each bit data of the 3 bits data is allocated to each threshold value distribution, comprising:
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a control unit that performs control such that the threshold value distribution is allocated by first data coding in which a first page, a second page, and a third page are each 1 bit and data is written to the non-volatile semiconductor memory, a first bit of the 3 bits data indicating data of the first page, a second bit thereof indicating data of the second page, and a third bit thereof indicating data of the third page; and an encoding unit that generates a first parity with a first size for user data stored in the first page, generates a second parity with a second size for user data stored in the second page, and generates a third parity with a third size for user data stored in the third page, wherein the control unit performs control such that the user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by the first data coding and performs control such that a portion of the second parity and a portion of the third parity are allocated to each threshold value by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit and are written to the non-volatile semiconductor memory.
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13. A memory control method that controls a non-volatile semiconductor memory which includes memory cells each storing 3 bits, and each bit data of the 3 bits data is allocated to each threshold value distribution, comprising:
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performing control such that the threshold value distribution is allocated by first data coding in which a first page, a second page, and a third page are each 1 bit and data is written to the non-volatile semiconductor memory, a first bit of the 3 bits data indicating data of the first page, a second bit thereof indicating data of the second page, and a third bit thereof indicating data of the third page; generating a first parity with a first size for user data stored in the first page, generating a second parity with a second size for user data stored in the second page, and generating a third parity with a third size for user data stored in the third page; and performing control such that the user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by the first data coding and performing control such that a portion of the second parity and a portion of the third parity are allocated to each threshold value by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit and are written to the non-volatile semiconductor memory.
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Specification