COMPUTER ARCHITECTURE WITH A HARDWARE ACCUMULATOR RESET
First Claim
Patent Images
1. A method performable by a processor including an accumulator, the method comprising:
- selecting at least one event, thereby producing at least one selected event;
generating a reset signal to the accumulator responsive to said at least one selected event; and
responsive to said reset signal, resetting the accumulator to zero or an initial value while avoiding breaking pipelined execution of the processor.
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Abstract
A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.
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Citations
18 Claims
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1. A method performable by a processor including an accumulator, the method comprising:
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selecting at least one event, thereby producing at least one selected event; generating a reset signal to the accumulator responsive to said at least one selected event; and responsive to said reset signal, resetting the accumulator to zero or an initial value while avoiding breaking pipelined execution of the processor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method performed by a system including a camera adapted to capture multiple image frames, the system including a processor, the method comprising:
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enabling inputting a plurality of image patches from said image frames; initiating a processing loop for processing said image patches; and resetting the accumulator of the processor while processing said processing loop while avoiding breaking pipelined execution of the processor. - View Dependent Claims (9)
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10. A system comprising:
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a processor including an accumulator; and logical circuitry configured to select at least one event to produce at least one selected event, to generate a reset signal to the accumulator responsive to said at least one selected event; and
responsive to said reset signal, to reset the accumulator to zero or an initial value while avoiding breaking pipelined execution of the processor. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification