METHOD FOR MONITORING THE COORDINATED EXECUTION OF SEQUENCED TASKS BY AN ELECTRONIC CARD COMPRISING AT LEAST TWO PROCESSORS SYNCHRONIZED TO TWO DIFFERENT CLOCKS

• US 20140033225A1
• Filed: 07/24/2013
• Published: 01/30/2014
• Est. Priority Date: 07/30/2012
• Status: Active Grant

• Current Assignee: Airbus Operations SAS (Airbus SE)
• Original Assignee: Airbus Operations SAS (Airbus SE)
• Inventors: Tost, Gilles, Roblero Martinez, David, Dejean, Thierry, Deneuville, Sophie, Marliere, Laurent, Blouin, Hlne
• Granted Patent: US 9,424,100 B2
• Time in Patent Office: Days
• US Class Current: 718/106
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 11/0715 in a system implementing multitasking multitasking per se G06F9/46
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0739 in a data processing system embedded in automotive or aircraft systems
• CPC Class Codes: G06F 11/0763 by bit configuration check, e.g. of formats or tags
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: H04W 56/00 Synchronisation arrangements

Abstract

A method for monitoring the coordinated execution of sequenced tasks by an electronic device including a main electronic card including at least one main processor synchronized to a main clock and at least one auxiliary electronic card including at least one auxiliary processor synchronized to an auxiliary clock, includes

• • emitting by the main processor of a coordination marker to the auxiliary processor at the start of each main time period;
  • emitting by the auxiliary processor of a response word formed on the basis of the last coordination marker received to the main processor at the end of each auxiliary time period;
  • validating by the main processor of the response word received with respect to the first coordination marker emitted; and
  • signaling by the main processor if the response word received is not valid so as to signal a defect of coordination of the auxiliary processor.

Claims

1. A method for monitoring the coordinated execution of sequenced tasks by an electronic device comprising a main electronic card comprising at least one main processor synchronized to a main clock of main time period and at least one auxiliary electronic card comprising at least one auxiliary processor synchronized to an auxiliary clock of auxiliary time period, the auxiliary clock being faster than the main clock, the sequenced tasks having to be carried out simultaneously by the processors, in which method:

over a determined main time period, the main processor executes a first sequenced task while the auxiliary processor executes instructions of the first sequenced task over a plurality of auxiliary time periods;

over the consecutive main time period, the main processor executes a second sequenced task;

said method comprising;

a step of emission by the main processor of a coordination marker to the auxiliary processor at the start of each main time period;

a step of emission by the auxiliary processor of a response word formed on the basis of the last coordination marker received to the main processor at the end of each auxiliary time period;

a step of validation by the main processor of the response word received with respect to the first coordination marker emitted, the validation step being carried out at the start of the consecutive time period before the emission of a new coordination marker; and

a step of signaling by the main processor if the response word received is not valid so as to signal a defect of coordination of the auxiliary processor.

2. The monitoring method as claimed in claim 1, wherein the auxiliary card and the main card are linked by at least one auxiliary communication link.

3. The monitoring method as claimed in claim 2, wherein the nature of the coordination marker is defined as a function of the topology of the auxiliary communication link to allow a highlighting of a current defect of said auxiliary communication link.

4. The monitoring method as claimed in claim 3, wherein the nature of the coordination marker is defined as a function of the topology of the auxiliary communication link to allow a highlighting a sticking of first and second consecutive bits of said auxiliary communication link.

5. The monitoring method as claimed in claim 1, wherein the coordination marker is a hexadecimal integer coded on 32 bits.

6. The monitoring method as claimed in claim 1, wherein the coordination markers are dispatched in an alternating manner.

7. The monitoring method as claimed in claim 6, wherein the coordination markers dispatched are two in number.

8. The monitoring method as claimed in claim 1, wherein the response word is the complement of the last coordination marker received.

9. The monitoring method as claimed in claim 1, wherein the main processor keeps only the last response word received.

10. The monitoring method as claimed in claim 1, wherein the electronic device comprises a second auxiliary electronic card comprising at least one auxiliary processor synchronized to an auxiliary clock of auxiliary time period, and wherein the main processor monitors the coordination of the execution of sequenced tasks on each of the at least one and the second auxiliary processor.

11. The monitoring method as claimed in claim 1, wherein the main electronic card comprises a second main processor synchronized to one and the same main clock of main time period as the at least one main processor, and wherein each of the at least one and the second main processor monitors the coordination of the execution of sequenced tasks on the auxiliary processor.