NETWORK INTERFACE DEVICE HAVING A SOLID-STATE SAFEGUARD APPARATUS FOR PRESERVING THE QUALITY OF PASSIVE OPERATION IN THE EVENT OF DISRUPTIVE OPERATIONAL CONDITIONS

• US 20140033264A1
• Filed: 08/16/2013
• Published: 01/30/2014
• Est. Priority Date: 11/14/2011
• Status: Active Grant

• Current Assignee: PPC Broadband Incorporated (Belden Inc.)
• Original Assignee: PPC Broadband Incorporated (Belden Inc.)
• Inventors: Alkan, Erdogan, Li, Yan, Bailey, Paul F.
• Granted Patent: US 9,832,533 B2
• Time in Patent Office: Days
• US Class Current: 725/127
• CPC Class Codes: H03H 7/185 comprising distributed impedance elements together with lumped impedance elements
• CPC Class Codes: H03H 7/48 Networks for connecting several sources or loads, working on the same frequency or frequency band, to a common load or source phase shifters providing two or more output signals H03H7/21
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 12/2892 characterised by the access multiplexer architecture
• CPC Class Codes: H04N 21/436 Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
• CPC Class Codes: H04N 21/61 Network physical structure; Signal processing H04B takes precedence
• CPC Class Codes: H04N 21/6118 involving cable transmission, e.g. using a cable modem
• CPC Class Codes: H04N 7/104 Switchers or splitters
• CPC Class Codes: H04N 7/17309 Transmission or handling of upstream communications

Abstract

A network interface device has a safeguard apparatus. The safeguard apparatus is operable in power on, power off, and degraded power conditions. In power on operation, the safeguard apparatus maintains the quality of active and passive branch communications. During power off and degraded power operation, the safeguard apparatus safeguards the quality of the passive communication path.

Claims

1. A network interface device operable to couple at least two subscriber devices to a cable television (CATV) network over which (a) downstream signals are transmittable to the at least two subscriber devices and (b) upstream signals are transmittable from the at least two subscriber devices, the at least two subscriber devices including at least one passive subscriber device and at least one active subscriber device, the network interface device comprising:

a signal splitter configured to separate CATV signals into passive branch signals and into active branch signals;

an active branch circuit, the active branch circuit including an active signal conditioner operable to modify the active branch signals sent through the active branch circuit to the at least one active subscriber device;

a passive branch circuit, wherein the passive branch signals are sendable through the passive branch circuit to the at least one passive subscriber device; and

a safeguard circuit operably coupled to the active branch circuit and the signal splitter, the safeguard circuit having a first mode and a second mode, the safeguard circuit configured to exchange the CATV signals between the CATV network and the at least one active subscriber device when in the first mode, wherein;

(a) the safeguard circuit is configured to perform signal reduction when in the second mode, (b) the safeguard circuit is configured to assume the first mode in response to sensing a normal operative condition of the network interface device and (c) the safeguard circuit is configured to assume the second mode in response to sensing an abnormal operative condition of the network interface device.

2. The network interface device of claim 1, wherein the safeguard circuit comprises a phase cancellation element, the phase cancellation element adapted to convert the CATV signals into a phase-delayed signal, the phase-delayed signal being out of phase with respect to a reference signal.

3. The network interface device of claim 2, wherein the phase cancellation element comprises a balun transformer.

4. The network interface device of claim 1, wherein the safeguard circuit comprises a solid-state configuration.

5. The network interface device of claim 1, wherein the safeguard circuit comprises:

(a) at least one field-effect transistor (FET), (b) at least one PIN diode and (c) at least one inductor.

6. A safeguard apparatus operable in a network interface device, the safeguard apparatus comprising:

an input node;

a first field-effect transistor (FET) having a drain node, a source node and a gate node;

a first PIN diode having a first PIN diode anode and a first PIN diode cathode; and

an output node;

wherein;

(a) the drain node of the first FET is operably coupled to the first PIN diode anode and to the input node, (b) the gate node of the first FET is operably coupled to a ground, and (c) the first PIN diode cathode is operably coupled to the output node.

7. The safeguard apparatus of claim 6, further comprising an anode inductor having a first anode inductor end and a second anode inductor end, wherein:

(a) the first anode inductor end is operably coupled to a voltage source and (b) the second anode inductor end is operably coupled to the first PIN diode anode.

8. The safeguard apparatus of claim 6, further comprising a gate resistor having a first gate resistor end and a second gate resistor end,

wherein the gate node of the first FET is operably coupled to the first gate resistor end, and

the second gate resistor end is operably coupled to the ground.

9. The safeguard apparatus of claim 6, further comprising:

a cathode resistor having a first cathode resistor end and a second cathode resistor end; and

a cathode inductor having a first cathode inductor end and a second cathode inductor end,

wherein the first cathode resistor end is operably coupled to the ground,

the second cathode resistor end is operably coupled to the first cathode inductor end, and

the second cathode inductor end is operably coupled to the first PIN diode cathode and operably coupled to the output node.

10. The safeguard apparatus of claim 6, further comprising a second PIN diode having a second PIN diode anode and a second PIN diode cathode,

wherein the first PIN diode cathode is operably coupled to the output node via the second PIN diode,

the second PIN diode anode is operably coupled to the output node, and

the second PIN diode cathode is operably coupled to the first PIN diode cathode.

11. The safeguard apparatus of claim 10, further comprising a second anode inductor having a first end and a second end, wherein:

(a) the first end of the second anode inductor is operably coupled to a voltage source and (b) the second end of the second anode inductor is operably coupled to the second PIN diode anode.

12. The safeguard apparatus of claim 6, further comprising a phase cancellation element having a first phase cancellation element end and a second phase cancellation element end, wherein:

(a) the first phase cancellation element end is operably coupled to the source node of the first FET and (b) the second phase cancellation element end is operably coupled to the ground.

13. The safeguard apparatus of claim 12, wherein the phase cancellation element comprises a balun transformer.

14. The safeguard apparatus of claim 6, wherein the safeguard apparatus comprises a solid-state configuration.

15. The safeguard apparatus of claim 6, further comprising a second FET having a second FET drain node, a second FET source node and a second FET gate node, wherein:

(a) the second FET drain node is operably coupled to the source node of the first FET, and (b) the second FET drain node is operably coupled to the first PIN diode anode and to the input node via the first FET.

16. The safeguard apparatus of claim 15, further comprising a gate resistor having a first gate resistor end and a second gate resistor end, wherein:

(a) the first gate resistor end is operably coupled to the second FET gate node and (b) the second gate resistor end is operably coupled to the ground.

17. The safeguard apparatus of claim 6, further comprising a source inductor having a first source inductor end and a second source inductor end, wherein:

(a) the first source inductor end is operably coupled to the source node of the first FET and operably coupled to the ground, and (b) the second source inductor end is operably coupled to a voltage source.

18. The safeguard apparatus of claim 17, where the voltage source is a control voltage provided by a fault sensing circuit.

19. A safeguard apparatus operable in a network interface device, the safeguard apparatus comprising:

an input node;

an anode inductor having a first anode inductor end and a second anode inductor end;

a first field-effect transistor (FET) having a drain node, a source node and a gate node;

a gate resistor having a first gate resistor end and a second gate resistor end;

a cathode inductor having a first cathode inductor end and a second cathode inductor end;

an cathode resistor having a first cathode resistor end and a second cathode resistor end;

a first PIN diode having a first PIN diode anode and a first PIN diode cathode; and

an output node,

wherein the drain node of the first FET is operably coupled (a) to the first PIN diode anode, (b) to the input node and (c) to the second anode inductor end,

the first anode inductor end is operably coupled to a voltage source,

the gate node of the first FET is operably coupled to the first gate resistor end,

the second gate resistor end is operably coupled to a ground,

the first cathode resistor end is operably coupled to the ground,

the second cathode resistor end is operably coupled to the first cathode inductor end, and

the second cathode inductor end is operably coupled to the first PIN diode cathode and operably coupled to the output node.

20. The safeguard apparatus of claim 19, further comprising:

a second FET having a second FET drain node, a second FET source node and a second FET gate node,

a second FET gate resistor having a plurality of ends; and

a source inductor having a first source inductor end and a second source inductor end,

wherein the second FET drain node is operably coupled to the first PIN diode anode and to the input node via the first FET,

the second FET drain node is operably coupled to the source node of the first FET,

an end of the second FET gate resistor is operably coupled to the second FET gate node,

another end of the second FET gate resistor is operably coupled to the ground,

the first source inductor end is operably coupled to the source node of the first FET and to the ground, and

the second source inductor end is operably coupled to the voltage source.

21. The safeguard apparatus of claim 20, further comprising:

a second PIN diode having a second PIN diode anode and a second PIN diode cathode, wherein;

(a) the second cathode inductor end and the first PIN diode cathode are operably coupled to the output node via the second PIN diode, (b) the second PIN diode anode is operably coupled to the output node, and (c) the second PIN diode cathode is operably coupled to first PIN diode cathode and to the second cathode inductor end; and

a second anode inductor having a first end and a second end, wherein the first end of the second anode inductor is operably coupled to the voltage source and the second end of the second anode inductor is operably coupled to the second PIN diode anode.

22. The safeguard apparatus of claim 19, further comprising a phase cancellation element having a first phase cancellation element end and a second phase cancellation element end, wherein:

(a) the first phase cancellation element end is operably coupled to the source node of the first FET, and (b) the second phase cancellation element end is operably coupled to the ground.

23. The safeguard apparatus of claim 22, further comprising:

a second PIN diode having a second PIN diode anode and a second PIN diode cathode, wherein;

(a) the second cathode inductor end and the first PIN diode cathode are operably coupled to the output node via the second PIN diode, (b) the second PIN diode anode is operably coupled to the output node, and (c) the second PIN diode cathode is operably coupled to first PIN diode cathode and to the second cathode inductor end; and

a second anode inductor having a first end and a second end, wherein the first end of the second anode inductor is operably coupled to the voltage source and the second end of the second anode inductor is operably coupled to the second PIN diode anode.