LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE

• US 20140034902A1
• Filed: 03/15/2013
• Published: 02/06/2014
• Est. Priority Date: 08/06/2012
• Status: Active Grant

• Current Assignee: Suzhou Lekin Semiconductor Company Limited
• Original Assignee: Jung Hyun Hwang, Oh Min Kwon
• Inventors: HWANG, Jung Hyun, Won, Jong Hak, Kwon, Oh Min
• Granted Patent: US 9,349,914 B2
• Time in Patent Office: Days
• US Class Current: 257/13
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/14 with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure

Abstract

Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer. The active layer includes (T+1) barrier layers, T well layers between the (T+1) barrier layers, and a first dummy layer between N well layers adjacent to the second conductive semiconductor layer and N barrier layers adjacent to the N well layers, in which T>N≧1.

Claims

1. A light emitting device comprising:

a first conductive semiconductor layer;

an active layer on the first conductive semiconductor layer; and

a second conductive semiconductor layer on the active layer,

wherein the active layer comprises;

(T+1) barrier layers;

T well layers between the (T+1) barrier layers; and

a first dummy layer between N well layers adjacent to the second conductive semiconductor layer and N barrier layers adjacent to the N well layers, in which T>

N≧

1.

2. The light emitting device of claim 1, wherein the active layer further comprises a second dummy layer between M well layers adjacent to the first conductive semiconductor layer and M barrier layers adjacent to the M well layers, in which N≧

M≧

1.

3. The light emitting device of claim 2, wherein the first dummy layer is disposed on one of a top surface and a bottom surface of the barrier layers.

4. The light emitting device of claim 2, wherein the second dummy layer is disposed on one of a top surface and a bottom surface of the barrier layers.

5. The light emitting device of claim 2, wherein the active layer further comprises a third dummy layer between a first barrier layer contacting the second conductive semiconductor layer and a first well layer contacting the first barrier layer.

6. The light emitting device of claim 5, wherein each of the first to third dummy layers has a thickness in a range of about 2 nm to about 4 nm.

7. The light emitting device of claim 5, wherein the first dummy layer is disposed on one of a top surface and a bottom surface of a second barrier layer contacting the first well layer.

8. The light emitting device of claim 5, wherein the active layer further comprises a fourth dummy layer between a third barrier layer contacting the first conductive semiconductor layer and a second well layer contacting the third barrier layer.

9. The light emitting device of claim 8, wherein each of the second and fourth dummy layers has a thickness in a range of about 1 nm to about 2 nm.

10. The light emitting device of claim 8, wherein the second dummy layer is disposed on one of a top surface and a bottom surface of a fourth barrier layer contacting the second well layer.

11. The light emitting device of claim 8, wherein at least one of the first to fourth dummy layers has a bandgap equal to a bandgap of the first barrier layer.

12. The light emitting device of claim 8, wherein at least one of the first to fourth dummy layers has a bandgap between a bandgap of the first well layer and a bandgap of the first barrier layer.

13. The light emitting device of claim 8, wherein at least one of the first to fourth dummy layers includes the same compound semiconductor material as a compound semiconductor material of the first barrier layer.

14. The light emitting device of claim 1, wherein the (T+1) barrier layers have equal thicknesses.

15. The light emitting device of claim 1, wherein the active layer generates a light having a peak wavelength of 450 nm or more.

16. A light emitting device comprising:

a substrate;

a first conductive semiconductor layer on the substrate;

an active layer on the first conductive semiconductor layer; and

a second conductive semiconductor layer on the active layer,

wherein the active layer comprises;

first to fourth barrier layers; and

first to third well layers between the first to fourth barrier layers, and wherein the first barrier layer contacts the first conductive semiconductor layer, the fourth barrier layer contacts the second conductive semiconductor layer, and the third and fourth barrier layers have thicknesses greater than thicknesses of the first and second barrier layers, respectively.

17. The light emitting device of claim 16, wherein the thickness of each of the first and second barrier layers is about 5 nm, and the thickness of each of the third and fourth barrier layers is about 7 nm.

18. The light emitting device of claim 16, wherein the thickness of each of the first and second barrier layers is about 6 nm, and the thickness of each of the third and fourth barrier layers is about 7 nm.

19. The light emitting device of claim 16, wherein the first conductive semiconductor layer is an N type semiconductor layer, and the second conductive semiconductor layer is a P type semiconductor layer.

20. A light emitting device package comprising:

a body;

first and second electrode lines on the body; and

a light emitting device on the body or one of the first and second electrode lines,

wherein the light emitting device comprises;

a first conductive semiconductor layer;

an active layer on the first conductive semiconductor layer; and

a second conductive semiconductor layer on the active layer, and

wherein the active layer comprises;

(T+1) barrier layers;

T well layers between the (T+1) barrier layers; and

a first dummy layer between N well layers adjacent to the second conductive semiconductor layer and N barrier layers adjacent to the N well layers, in which T>

N≧

1.