Semiconductor Devices and Methods of Manufacturing the Same

• US 20140035058A1
• Filed: 07/12/2013
• Published: 02/06/2014
• Est. Priority Date: 07/31/2012
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Min, Ji-Young, Nam, Gab-Jin, Chung, Eun-Ae, Choi, Jung-Dal, Kim, Jin-Soak, Baek, Sung-Kweon
• Application Number:
  US13/940,440
• Publication Number:
  US 20140035058A1
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

Methods of manufacturing a semiconductor device include forming a thin layer on a substrate including a first region and a second region and forming a gate insulating layer on the thin layer. A lower electrode layer is formed on the gate insulating layer and the lower electrode layer disposed in the second region is removed to expose the gate insulating layer in the second region. Nitrogen is doped into an exposed portion of the gate insulating layer and the thin layer disposed under the gate insulating layer. An upper electrode layer is formed on the lower electrode layer remaining in the first region and the exposed portion of the gate insulating layer. The upper electrode layer, the lower electrode layer, the gate insulating layer and the thin layer are partially removed to form first and second gate structures in the first and second regions. The process may be simplified.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a thin layer on a substrate including a first region and a second region;

forming a gate insulating layer on the thin layer;

doping nitrogen into a portion of the gate insulating layer and a portion of the thin layer disposed under the gate insulating layer in the second region; and

forming first and second gate structures in the first and second regions, respectively.

2. The method according to claim 1, wherein forming the first and second gate structures comprises:

forming a lower electrode layer on the gate insulating layer in the first region; and

forming an upper electrode layer on the lower electrode layer in the first region and the gate insulating layer in the second region.

3. The method according to claim 2, wherein forming the lower electrode layer on the gate insulating layer in the first region comprises:

forming the lower electrode layer on the gate insulating layer; and

removing a portion of the lower gate electrode layer that corresponds to the second region to expose a portion of the gate insulating layer in the second region.

4. The method according to claim 2, wherein forming the first and second gate structures further comprises partially removing the upper electrode layer, the lower electrode layer, the gate insulating layer and the thin layer to form first and second gate structures in the first and second regions, respectively.

5. The method according to claim 2, further comprising forming a hard mask on the lower electrode in the first region after forming the lower electrode layer,

and further comprising removing the hard mask before forming the upper electrode layer,

wherein removing the lower electrode layer disposed in the second region includes etching the lower electrode layer using the hard mask as an etching mask,

and wherein doping nitrogen is performed using the hard mask as a nitrogen doping mask.

6. The method according to claim 5, wherein forming the hard mask comprises:

forming a hard mask layer on the lower electrode layer; and

etching the hard mask layer through a photolithography process.

7. The method according to claim 3, further comprising forming a conductive layer on the gate insulating layer before forming the lower electrode layer.

8. The method according to claim 7, wherein removing the lower electrode layer disposed in the second region further comprises removing the conductive layer disposed in the second region.

9. The method according to claim 7, wherein the conductive layer disposed in the second region is exposed after removing the lower electrode layer disposed in the second region.

10. The method according to claim 2, wherein the lower electrode layer is formed to include a conductive material having a work function between about 4.5 eV and about 5.2 eV.

11. The method according to claim 1, wherein doping nitrogen includes performing a plasma nitridation process and/or a rapid thermal nitridation process.

12. The method according to claim 1, wherein doping nitrogen is performed under an atmosphere including a nitrogen gas or an ammonia gas.

13. The method according to claim 1, wherein forming the thin layer on the substrate comprises thermally oxidizing a surface of the substrate.

14. The method according to claim 1, after forming the first and second gate structures, further comprising,

forming first and second spacers on side walls of the first and second gate structures, respectively;

and

forming first and second impurity regions on upper portions of the substrate near the first and second gate structures, respectively, by doping impurities into the upper portions of the substrate using the first and second gate structures as impurity doping masks.

15. The method according to claim 14, wherein doping the impurities into the upper portions of the substrate comprises:

doping p-type impurities into the upper portion of the substrate near the first gate structure; and

doping n-type impurities into the upper portion of the substrate near the second gate structure.

16. The method according to claim 1, further comprising, before forming the thin layer:

forming dummy gate structures and spacers in the first region and the second region of the substrate;

forming impurity regions at the upper portions of the substrate near the dummy gate structures by doping impurities into the upper portions of the substrate using the dummy gate structures and the spacers as impurity doping masks; and

removing the dummy gate structures.

17. A semiconductor device, comprising:

a semiconductor substrate comprising a first region and a second region;

a PMOS transistor including a first gate structure and a first impurity region, a first gate structure being disposed in the first region of the substrate, the first gate structure including a first thin layer pattern, a first gate insulating layer pattern, a lower gate electrode and a first upper gate electrode, the first impurity region being formed at an upper portion of the substrate near the first gate structure; and

a NMOS transistor including a second gate structure and a second impurity region, the second gate structure being disposed in the second region of the substrate, the second gate structure including a second thin layer pattern, a second gate insulating layer pattern and a second upper gate electrode, the second impurity region being formed at the upper portion of the substrate near the second gate structure,

wherein the first thin layer pattern includes a first nitrogen concentration and the and the second thin layer pattern includes a second nitrogen concentration that is greater than the first nitrogen concentration.

18. The semiconductor device according to claim 17, wherein the lower gate electrode includes a conductive material having a work function between about 4.5 eV and about 5.2 eV.

19. The semiconductor device according to claim 17, wherein NMOS transistor including the second thin layer pattern has a voltage value corresponding to time dependent dielectric breakdown that is positively correlated with a nitrogen concentration of the second thin layer pattern.

20. The semiconductor device according to claim 17, wherein PMOS transistor including the first thin layer pattern has a voltage value corresponding to negative bias temperature instability that is negatively correlated with a nitrogen concentration of the first thin layer pattern.