CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE

• US 20140035154A1
• Filed: 08/02/2012
• Published: 02/06/2014
• Est. Priority Date: 08/02/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Geitner, Ottmar, Hartner, Walter, Wojnowski, Maciej, Wachter, Ulrich, Bauer, Michael, Stueckjuergen, Andreas
• Granted Patent: US 8,669,655 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/21 of an individual HDI interconnect
• CPC Class Codes: H01L 2224/2105 Shape
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73151 on different surfaces
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01026 : Iron [Fe]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1304 : Transistor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/142 : HF devices
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.

Claims

1. A chip package comprising:

a chip comprising at least one contact pad formed on a chip front side;

an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and

at least one electrical interconnect formed through the encapsulation material,

wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side being to face a substrate.

2. The chip package according to claim 1,

wherein the chip comprises a semiconductor logic chip, and

wherein the semiconductor logic chip comprises at least one of an application specific integrated circuit chip, a driver, a controller, and a sensor.

3. The chip package according to claim 1,

wherein the chip comprises a semiconductor power chip, and

wherein the power semiconductor chip comprises at least one of a power transistor, a power MOS transistor, a power bipolar transistor, a power field effect transistor, a power insulated gate bipolar transistor, a thyristor, a MOS controlled thyristors, a silicon controlled rectifier, a power schottky diode, a silicon carbide diode, and a gallium nitride device.

4. The chip package according to claim 1,

wherein the chip comprises an active chip region at the chip front side, and

wherein the active chip region is configured to at least one of transmit a signal and receive a signal.

5. The chip package according to claim 4,

wherein the signal comprises an electromagnetic wave signal.

6. The chip package according to claim 5,

wherein the electromagnetic wave signal comprises a radio frequency signal.

7. The chip package according to claim 1,

wherein the chip comprises an active chip region at the chip front side, and

wherein the active chip region comprises a sensing region configured to at least one of receive an external stimulus to be measured by the chip and sense an external stimulus to be measured by the chip.

8. The chip package according to claim 1,

wherein the encapsulation material is formed over one or more sidewalls of the chip and the chip front side.

9. The chip package according to claim 1,

wherein the encapsulation material comprises an electrically insulating material.

10. The chip package according to claim 1,

wherein the encapsulation material comprises at least one of filled or unfilled epoxy, pre-impregnated composite fibers, reinforced fibers, laminate, a mold material, a thermoset material, and a thermoplastic material.

11. The chip package according to claim 1,

wherein the at least one contact pad comprises a first contact pad and a second contact pad, and

wherein the first contact pad is electrically insulated from the second contact pad by passivation material formed on the chip front side.

12. The chip package according to claim 11,

wherein the passivation material comprises at least one of silicon nitride, silicon dioxide, and polyimide.

13. The chip package according to claim 1, further comprising:

at least one contact pad extension region formed over the at least one contact pad;

wherein the at least one electrical interconnect is electrically connected to the at least one contact pad via the at least one contact pad extension region.

14. The chip package according to claim 1, further comprising:

electrically insulating material formed over the encapsulation material at the chip package first side and over the chip front side; and

at least one electrically conductive redistribution layer formed through the electrically insulating material;

wherein the electrically conductive redistribution layer electrically connects the at least one contact pad to the at least one electrical interconnect.

15. The chip package according to claim 1,

wherein the chip comprises a chip back side metallization layer formed on a chip back side, and

wherein the chip back side metallization layer is electrically connected to at least one further solder structure formed at a chip package second side.

16. The chip package according to claim 15, further comprising:

an extension layer formed over the chip back side metallization layer,

wherein the chip back side metallization is electrically connected to the at least one further solder structure via the extension layer.

17. The chip package according to claim 1, further comprising:

an extension layer formed over the chip back side,

wherein the extension layer is electrically connected to at least one further solder structure formed at the chip package second side.

18. The chip package according to claim 1, further comprising:

at least one further electrically conductive redistribution layer formed over the chip package second side,

wherein the at least one further redistribution layer electrically connects the at least one electrical interconnect to at least one solder structure arranged on a chip package second side.

19. The chip package according to claim 1,

wherein the chip package first side is formed over the chip front side;

and

wherein the chip package second side is formed over a chip back side.

20. The chip package according to claim 1,

wherein the at least one electrical interconnect is formed in at least one through-hole formed in the encapsulation material between the chip package first side and the chip package second side.

21. The chip package according to claim 20,

wherein the at least one electrical interconnect comprises electrically conductive material deposited in the at least one through-hole.

22. The chip package according to claim 1,

wherein the at least one solder structure comprises at least one of solder balls, solder bumps, and ribbed interconnecting structures.

23. The chip package according to claim I, further comprising:

a solder stop layer formed at the chip package second side,

wherein the solder stop layer is formed over the encapsulation material and the chip back side.

24. A method for manufacturing a chip package, the method comprising:

at least partially surrounding a chip comprising at least one contact pad formed on a chip front side with encapsulation material, the encapsulation material covering the at least one contact pad; and

forming at least one electrical interconnect through the encapsulation material, the at least one electrical interconnect electrically redirecting the at least one contact pad from a chip package first side to at least one solder structure formed over a chip package second side at a chip back side being to face a substrate.