NOISE RESISTANT REGULATOR

• US 20140035548A1
• Filed: 03/15/2013
• Published: 02/06/2014
• Est. Priority Date: 08/06/2012
• Status: Active Grant

• Current Assignee: Peter Oaklander
• Original Assignee: Peter Oaklander
• Inventors: Oaklander, Peter
• Granted Patent: US 9,231,463 B2
• Time in Patent Office: Days
• US Class Current: 323/283
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/14 Arrangements for reducing ripples from dc input or output
• CPC Class Codes: H02M 1/44 Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 7/537 using semiconductor devices only, e.g. single switched pulse inverters
• CPC Class Codes: H03K 17/063 in field-effect transistor switches

Abstract

A converter for supplying a regulated voltage from an input to a load is disclosed. The converter supplies a regulated DC voltage from an input to a load using a power switch driven by a gate driver. It also includes a control loop for carrying a load condition signal and a control signal. The converter also includes a controller located on the control loop that generates the control signal based on the load signal. The controller is located on a first integrated circuit. The gate driver is located on a second integrated circuit. The load condition signal is encoded on the first integrated circuit and is decoded on the second integrated circuit.

Claims

1. A noise resistant DC to DC converter comprising:

a power switch used to supply a regulated DC voltage to a load, the power switch driven by a gate driver;

a control loop carrying a load condition signal and a control signal; and

a controller located on the control loop that generates the control signal based on the load condition signal;

wherein;

the controller is located on a first integrated circuit;

the gate driver is located on a second integrated circuit; and

the load condition signal is encoded on the second integrated circuit, and is decoded on the first integrated circuit.

2. The noise resistant DC to DC converter of claim 1, wherein the load condition signal is encoded using a differential encoding.

3. The noise resistant DC to DC converter of claim 2, wherein the differential encoding is an LVDS encoding.

4. The noise resistant DC to DC converter of claim 1, further comprising:

an analog to digital converter located on the second integrated circuit;

an encoder located on the first integrated circuit, the encoder encoding the control signal and embedding a synchronization signal in the control signal; and

a decoder located on the second integrated circuit, the decoder decoding the control signal and providing the synchronization signal to the analog to digital converter.

5. The noise resistant DC to DC converter of claim 1, further comprising:

a delta sigma modulator located on the second integrated circuit, the delta sigma modulator encoding the load condition signal, and producing a bit stream that contains the load condition signal;

a decimation filter located on the first integrated circuit, the decimation filter being used to resolve the bit stream.

21. The noise resistant DC to DC converter of claim 1, further comprising:

a digital pulse generator for decoding a digital bit stream from the controller and producing a modulated signal for the gate driver;

wherein the digital pulse generator is located on the second integrated circuit; and

wherein the modulated signal is a pulse width modulated signal or a pulse frequency modulated signal.

6. An apparatus comprising:

a converter for supplying a power from an input to a load;

a feedback path for controlling the converter, at least a portion of the feedback path carrying a load condition signal;

a decoder for decoding an encoded load condition signal to produce a decoded load condition signal, the decoded load condition signal being used to generate a control signal to control the converter; and

an encoder for encoding the load condition signal to produce the encoded load condition signal, the load condition signal and the encoded load condition signal both representing a condition of the load;

wherein the decoder is located on a first integrated circuit and the encoder is located on a second integrated circuit.

7. The apparatus of claim 6, wherein:

the encoder is a digital encoder;

the feedback path additionally carries a second load condition signal; and

the encoder embeds the first load condition signal and the second load condition signal in the encoded load condition signal.

8. The apparatus of claim 6, wherein the encoder utilizes a noise resistant encoding.

9. The apparatus of claim 6, wherein the encoder applies a differential encoding;

and the load condition signal changes from a single ended signal to a differential signal when it transfers through the encoder.

10. The apparatus of claim 9, wherein the differential encoding is an LVDS encoding.

11. The apparatus of claim 6, wherein:

the encoder applies a digital encoding; and

the load condition signal changes from an analog signal to a digital signal when it transfers through the encoder.

12. The apparatus of claim 11, further comprising:

a second power converter for supplying power to the load; and

a second encoder for encoding a second load condition signal;

wherein the first and second encoders encode the first and second load condition signals to be out of phase such that they can be transmitted serially.

13. The apparatus of claim 12, wherein the first and second load condition signals are differentially encoded and transmitted serially on a single pair of differential circuit traces.

14. The apparatus of claim 12, further comprising:

an analog to digital converter located on the second integrated circuit;

an encoder located on the first integrated circuit, the encoder encoding the control signal and embedding a synchronization signal in the control signal; and

a decoder located on the second integrated circuit, the decoder decoding the control signal and providing the synchronization signal to the analog to digital converter.

15. The apparatus of claim 14, wherein the encoder utilizes an LVDS encoding.

22. The apparatus of claim 6, further comprising

a digital pulse generator for decoding a digital signal and producing a modulated signal for a gate driver;

and

a power switch controlled by the gate driver and coupled between the input and the load;

wherein the digital pulse generator, the gate driver, and the power switch are located on the second integrated circuit; and

wherein the modulated signal is a pulse width modulated signal or a pulse frequency modulated signal.

16. An apparatus comprising:

a converter for providing a regulated voltage to a load;

a control loop for routing a signal, the control loop controlling the converter;

an encoder for encoding the signal to produce an encoded signal; and

a decoder for decoding the encoded signal to produce a decoded signal;

wherein the encoder and the decoder are located on different integrated circuits; and

wherein the signal and the decoded signal have the same informational content.

17. The apparatus of claim 16, further comprising:

a second decoder located on the same integrated circuit as the encoder; and

a second encoder located on the same integrated circuit as the decoder;

wherein;

the second encoder encodes a converter control signal and combines the converter control signal with a synchronization signal; and

the second decoder decodes the converter control signal and provides the synchronization signal to the encoder.

18. The apparatus of claim 16, wherein the signal is a load condition signal.

19. The apparatus from claim 18, wherein the encoder comprises a delta sigma modulator and the decoder comprises a decimation filter.

20. The apparatus of claim 19, further comprising:

a first power switch for providing a current signal to the load during a first phase, the first power switch being controlled via the converter control signal;

a second power switch for providing a second current signal to the load during a second phase; and

a second signal for controlling the converter via the second power switch, the second signal being a second converter control signal;

wherein the first and second converter control signals are digital encodings of PWM signals.

23. The apparatus of claim 16, further comprising:

a digital pulse generator for decoding a digital bit stream generated by the encoder and producing a modulated signal for a gate driver;

wherein the digital pulse generator and the decoder are located on the same integrated circuit; and

wherein the modulated signal is a pulse width modulated signal or a pulse frequency modulated signal.

24. A method for controlling a DC-DC converter comprising:

generating a load condition signal and a control signal;

generating the control signal based on the load condition signal using a controller, the controller being implemented on a first integrated circuit;

driving a power switch using a gate driver and the control signal, the gate driver being located on a second integrated circuit;

encoding the load condition signal on one of the second integrated circuit and a third integrated circuit co-packaged with the second integrated circuit; and

decoding the load condition signal on the first integrated circuit;

wherein the encoding results in a differential signal representative of the load condition signal.

25. The method of claim 24, wherein the encoding digitally encodes the load condition signal.

26. The method of claim 24, wherein the encoding is an LVDS encoding.

27. The method of claim 24, further comprising:

encoding the control signal on the first integrated circuit using an encoder;

embedding a synchronization signal in the control signal using the encoder;

decoding the control signal using a decoder on one of the second integrated circuit and a fourth integrated circuit co-packaged with the second integrated circuit; and

providing the synchronization signal from the decoder to a control circuit located on one of the second integrated circuit and the fourth integrated circuit.

28. The method of claim 27 wherein the controls circuit is an analog to digital converter.