MEMORY DEVICE HAVING A DIFFERENT SOURCE LINE COUPLED TO EACH OF A PLURALITY OF LAYERS OF MEMORY CELL ARRAYS

• US 20140036586A1
• Filed: 09/26/2013
• Published: 02/06/2014
• Est. Priority Date: 03/08/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: GODA, Akira, LIU, Zengtao
• Granted Patent: US 9,202,574 B2
• Time in Patent Office: Days
• US Class Current: 365/185.02
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

In an embodiment, a memory device may have a plurality of layers of memory cell arrays. Each layer may have a plurality of strings of memory cells and a different source line coupled to each layer of the plurality of layers.

Claims

1. A memory device comprising:

a plurality of layers of memory cell arrays, each layer comprising;

a plurality of strings of memory cells; and

a different source line coupled to each layer of the plurality of layers.

2. The memory device of claim 1 and further including an access line coupled to a particular row of memory cells wherein the access line is common to the particular row of each of the plurality of layers.

3. The memory device of claim 1 and further including a different data line coupled to each layer of the plurality of layers wherein the memory device is configured to select a particular layer responsive to biasing of a respective one of the data lines.

4. The memory device of claim 1 and further including a select gate source line that is common to a particular one of the select gate drain transistors for each of the plurality of layers.

5. The memory device of claim 1 and further including a select gate drain line that is common to a particular one of the select gate drain transistors for each of the plurality of layers of memory cell arrays.

6. The memory device of claim 1 wherein the memory device is configured to bias each different source line with a respective source line voltage responsive to a programming rate for that respective layer.

7. The memory device of claim 1 wherein the memory device is configured to shift a target threshold voltage range of a layer responsive to a programming rate for that layer.

8. The memory device of claim 1, further comprising:

a different data line coupled to each layer of the plurality of layers;

wherein a first layer of the plurality layers comprises a plurality of first select transistors coupled to the data line coupled to the first layer of the plurality layers, wherein each first select transistor of the plurality of first select transistors is configured to selectively couple a respective one of the strings of memory cells of the plurality of strings of memory cells of the first layer to the data line coupled to the plurality of first select transistors;

wherein a second layer of the plurality layers comprises a plurality of second select transistors coupled to the data line coupled to the second layer of the plurality layers, wherein each second select transistor of the plurality of second select transistors is configured to selectively couple a respective one of the strings of memory cells of the plurality of strings of memory cells of the second layer to the data line coupled to the plurality of second select transistors; and

wherein each of first select transistors of the plurality of first select transistors is coupled to a respective one of the second select transistors of the plurality of second select transistors by a control line.

9. The memory device of claim 1, wherein the memory device is coupled to a controller.

10. A memory device comprising:

a plurality of layers of memory cell arrays, each layer comprising;

a plurality of strings of memory cells; and

a different source line coupled to a different group of layers of the plurality of layers, wherein each group of layers comprises at least one of the layers.

11. The memory device of claim 10 wherein the memory device is configured to bias each different source line with a source line voltage that is responsive to a programming rate for its respective group of layers.

12. The memory device of claim 10 and further including a plurality of data lines, a respective data line coupled to each layer of the plurality of layers wherein the memory device is configured to select a respective layer responsive to biasing of a respective one of the data lines and further wherein the data lines are grouped according to the plurality of layers coupled to a particular source line and the data lines within a particular group at substantially the same voltage.

13. The memory device of claim 12 wherein the memory device is configured to bias data lines coupled to a particular group of layers having a relatively slower programming rate at a higher voltage than data lines coupled to a group of layers having a relatively faster programming rate.

14. A memory device comprising:

a plurality of layers of memory cell arrays, each layer comprising;

a plurality of strings of memory cells;

a different source line coupled to each layer of the plurality of layers; and

a different data line coupled to each layer of the plurality of layers so that the plurality of strings in each layer is between the bit line and the source line coupled to that layer.

15. The memory device of claim 14,

wherein each layer of the plurality of layers comprises a plurality of first select transistors and a plurality of second select transistors;

wherein in each layer of the plurality of layers, a first select transistor of the plurality of first select transistors of that layer is coupled between a respective one of the strings of memory cells of the plurality of strings of memory cells of that layer and the source line coupled to that layer; and

wherein in each layer of the plurality of layers, a second select transistor of the plurality of second select transistors of that layer is coupled between a respective one of the strings of memory cells of the plurality of strings of memory cells of that layer and the data line coupled to that layer.

16. The memory device of claim 15, further comprising a first control line that is common to each of the layers and that is coupled to the plurality of first select transistors in each of the layers.

17. The memory device of claim 16, further comprising a plurality of second control lines, wherein each second control line of the plurality of second control lines is common to each of the layers, each second control line of the plurality of second control lines coupled to one of the second select transistors from each layer.

18. The memory device of claim 14, further comprising a plurality of access lines, wherein each access line of the plurality of access lines is common to each of the layers, each access line of the plurality of access lines commonly coupled to one memory cell in each string of memory cells in each layer.

19. The memory device of claim 14 wherein the memory device is configured to bias each different source line with a respective source line voltage responsive to a programming rate for that respective layer.

20. The memory device of claim 14 wherein the memory device is configured to bias each different source line with a respective source line voltage and each different data line with a respective data line voltage so that a difference between the respective source line voltage and the respective data line voltage is the same for each layer.