ENCRYPTION PROCESSING DEVICE AND METHOD

• US 20140037089A1
• Filed: 06/17/2013
• Published: 02/06/2014
• Est. Priority Date: 08/02/2012
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: ITOH, Kouichi, TAKENAKA, Masahiko
• Application Number:
  US13/919,299
• Publication Number:
  US 20140037089A1
• Time in Patent Office: Days
• US Class Current: 380/46
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/04 Masking or blinding
• CPC Class Codes: H04L 2209/046 of operations, operands or results of the operations
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/004 for fault attacks
• CPC Class Codes: H04L 9/0869 involving random numbers or seeds
• CPC Class Codes: H04L 9/3271 using challenge-response

Abstract

An encryption processing device includes: a memory configured to store a first secret key and a first agitation value operated with the first secret key; and a processor coupled to the memory and configured to: receive a first random number, generate a second agitation key based on the first secret key and the first agitation value, generate a first encryption information based on the second secret key and the first random number, update the first agitation value stored in the memory, and output the first agitation value and the first encryption information.

Claims

1. An encryption processing device comprising:

a memory configured to store a first secret key and a first agitation value operated with the first secret key; and

a processor coupled to the memory and configured to;

receive a first random number,

generate a second agitation key based on the first secret key and the first agitation value,

generate a first encryption information based on the second secret key and the first random number,

update the first agitation value stored in the memory, and

output the first agitation value and the first encryption information.

2. The encryption processing device according to claim 1, wherein the processor is configured to output the first agitation value and the first encryption information to a device authenticating the authentication chip, and

wherein the device transmits the first random number to the authentication chip, receives the first agitation value and the first encryption information, generates a fourth secret key based on the first agitation value and a third secret key read out from the device memory, and executes authentication of the authentication chip based on the fourth secret key, the first encryption information, and the first random number.

3. The encryption processing device according to claim 2, wherein the processor is configured to generate the first encryption information by operating an encryption function on the second secret key and the first random number, and

wherein the device generates a second random number by operating a decryption function, which is the inverse function of the encryption function, on the fourth secret key and the first encryption information, and authenticates the authentication chip based on the comparison result of comparing the first random number and the second random number.

4. The encryption processing device according to claim 2, wherein the processor is configured to generate the first encryption information by operating an encryption function on the second secret key and the first random number, and

wherein the device generates a second random number by operating the encryption function on the fourth secret key and the first random number, and authenticates the authentication chip based on the comparison result of comparing the second random number and the first encryption information.

5. The encryption processing device according to claim 2, wherein the processor is configured to:

generate a third random number,

authenticate devices based on a response from the device corresponding to the third random number,

transmit the third random number to the device, and

receive the response from the device.

6. The encryption processing device according to claim 5, wherein the response includes a second encryption information related to the third random number, and a second agitation value used to generate the second encryption information, and

wherein the processor is configured to generate a fifth secret key based on the first secret key and the second agitation value, and

authenticate the device based on the fifth secret key, the second encryption information, and the third random number.

7. The encryption processing device according to claim 6, wherein the device generates the second encryption information by operating an encryption function on the second agitation value, a sixth secret key generated from the third secret key, and the third random number, and

wherein the processor is configured to authenticate the device based on the comparison result of the third random number and a fourth random number generated by operating a decryption function, which is the inverse function of the encryption function, on the fifth secret key and the second encryption information.

8. The encryption processing device according to claim 6, wherein the device generates the second encryption information by operating an encryption function on the third random number and a sixth secret key from the second agitation value and the third secret key, and

wherein the processor is configured to authenticate the device based on the comparison result of the second encryption information and a fourth random number generated by operating an encryption function on the fifth secret key and the third random number.

9. The encryption processing device according to claim 1, further comprising:

a non-volatile storage,

wherein the processor is configured to;

generate the second encryption information by operating an agitation function on the first secret key and the first agitation value,

store the second secret key into the non-volatile storage, and

update the second secret key by operating an inverse agitation function, which is the inverse of the agitation function, on the second secret key.

10. The encryption processing device according to claim 1, further comprising:

a non-volatile storage,

wherein the processor is configured to;

store the second secret key into the a non-volatile storage, and

read out all bits of the second secret key within one cycle.

11. The encryption processing device according to claim 1, further comprising:

a non-volatile storage,

wherein the processor is configured to write all bits of the second secret key to the non-volatile storage within one cycle.

12. The encryption processing device according to claim 1, further comprising:

a non-volatile storage,

wherein the processor is configured to perform at least one of writing processing to the non-volatile storage and reading processing from the non-volatile storage using a non-volatile flip-flop.

13. The encryption processing device according to claim 9, wherein the processor is configured to:

designate the first secret key and the first agitation value as input values,

designate the second secret key as an output value, and

operate a mask generating function as the agitation function, and

wherein the mask generating function includes a nature in which when even one bit of the input values change, at least a plurality of bits of the output value also changes, a nature in which the input value is not obtainable from the output value, and a nature in which the bit length of the input value and the output value are adjustable as desired.

14. The encryption processing device according to claim 9, wherein the processor is configured to:

designate a bit combination result of the higher half bits of the first secret key and the first agitation value and the lower half bits of the same as the input value, and

designate the result of operating a mask generating function as the agitation function on the input value as the output value, and

wherein the mask generating function includes a nature in which when even one bit of the input values change, at least a plurality of bits of the output value also changes, a nature in which the input value is not obtainable from the output value, and a nature in which the bit length of the input value and the output value are adjustable as desired.

15. The encryption processing device according to claim 1, wherein the processor is configured to mask the first secret key with a mask value.

16. The encryption processing device according to claim 15, wherein the processor is configured to:

perform pre-complication processing,

designate the first agitation value and a masked secret key obtained by executing the masking processing on the mask value and the first secret key as the input value,

perform a bit transposing processing determined by the first secret key and the first agitation value on the input value,

obtain the output value dependent on only the first secret key and the first agitation value, and

operate the mask generating function on the output value.

17. An encryption processing method executed by an encryption processing device, the encryption processing method comprising:

receiving a first random number;

storing a first secret key and a first agitation value operated with the first secret key in a memory;

generating a second secret key based on the first secret key and the first agitation value;

generating a first encryption information based on the second secret key and the first random number;

updating the first agitation value stored in the memory; and

outputting the first encryption information and the first agitation value.

18. A readable recording medium storing an encryption processing program including a process and for causing an encryption processing device execute the program, the process comprising:

receiving a first random number;

storing a first secret key and a first agitation value operated with the first secret key in a memory;

generating a second secret key based on the first secret key and the first agitation value;

generating a first encryption information based on the second secret key and the first random number;

updating the first agitation value stored in the memory; and

outputting the first agitation value and the first encryption information.