STACKED MEMORY DEVICE WITH HELPER PROCESSOR

• US 20140040532A1
• Filed: 08/06/2012
• Published: 02/06/2014
• Est. Priority Date: 08/06/2012
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Loh, Gabriel H., O'Connor, James M., Ignatowski, Michael, Jayasena, Nuwan S., Watanabe, Yasuko
• Application Number:
  US13/567,958
• Publication Number:
  US 20140040532A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: H01L 2224/08 of an individual bonding area
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73251 on different surfaces
• CPC Class Codes: H01L 2224/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a helper processor that executes instructions to perform tasks in response to a task request from the processor devices or otherwise on behalf of the other processor devices. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the processor devices. The memory interface operates to perform memory accesses for the processor devices and for the helper processor. By virtue of the helper processor'"'"'s tight integration with the stacked memory layers, the helper processor may perform certain memory-intensive operations more efficiently than could be performed by the external processor devices.

Claims

1. A system comprising:

an integrated circuit (IC) package comprising;

a set of stacked memory layers comprising memory cell circuitry; and

a set of one or more logic layers electrically coupled to the set of stacked memory layers, the set of one or more logic layers comprising a helper processor coupled to the memory cell circuitry of the set of stacked memory layers and comprising a memory interface coupled to the helper processor and coupleable to a processor device external to the IC package, the memory interface to perform memory accesses for the external processor device and to perform memory accesses for the helper processor.

2. The system of claim 1, wherein the set of one or more logic layers comprises:

a first logic layer comprising the helper processor; and

a second logic layer comprising the memory interface.

3. The system of claim 1, wherein the helper processor comprises a first processor core to execute instructions in accordance with a first instruction set architecture (ISA) and a second processor core to execute instructions in accordance with a second ISA.

4. The system of claim 3, wherein the first processor core comprises a central processing unit (CPU) core and the second processor core comprises a graphics processing unit (GPU) core.

5. The system of claim 1, wherein the helper processor is to execute instructions stored in the IC package.

6. The system of claim 5, wherein at least a portion of the instructions are stored in a non-volatile memory of the IC package.

7. The system of claim 5, wherein at least a portion of the instructions are stored in the memory cell circuitry.

8. The system of claim 5, wherein the instructions include instructions to manipulate the helper processor to perform at least one operation on a data structure stored in the memory cell circuitry and to provide for output to the external processor device a result of the at least one operation on the data structure.

9. The system of claim 5, wherein the instructions include instructions to manipulate the helper processor to execute an interrupt handling routine responsive to an interrupt.

10. The system of claim 5, wherein the instructions include instructions to manipulate the helper processor to execute at least one thread.

11. The system of claim 5, wherein the instructions include instructions to manipulate the helper processor to store at the memory cell circuitry a value representing a result of a computation performed by a first external processor device and to manipulate the helper processor to access the value from the memory cell circuitry and output the value to a second external processor device in response to a request from the second external processor device for the result of the computation from the first external processor.

12. The system of claim 5, wherein the instructions include instructions to manipulate the helper processor to recalculate a result of a computation performed by a first external processor device by accessing data for the computation from the memory cell circuitry and to manipulate the helper processor to output the result to a second external processor device in response to a request from the second external processor device for the result of the computation from the first external processor.

13. The system of claim 1, wherein the set of stacked memory layers and the set of one or more logic layers are disposed in a stacked configuration whereby the memory interface is connected to the stacked memory layers via a set of through silicon vias.

14. The system of claim 1, wherein the set of stacked memory layers and the set of one or more logic layers are disposed in a side-split arrangement whereby memory interface is connected to the stacked memory layers via an interposer.

15. The system of claim 1, further comprising:

the external processor device; and

an inter-processor interconnect coupled to the external processor device and coupled to the memory interface.

16. A computer readable medium storing code executable to adapt at least one computer system to perform a portion of a process to fabricate at least part of the IC package of claim 1.

17. A method comprising:

providing an integrated circuit (IC) package comprising a set of stacked memory layers comprising memory cell circuitry, and comprising a set of one or more logic layers electrically coupled to the set of stacked memory layers, the set of one or more logic layers comprising a helper processor coupled to the memory cell circuitry of the set of one or more stacked memory layers and comprising a memory interface coupled to the helper processor and coupled to a processor device external to the IC package;

operating the memory interface to perform memory accesses for at least the external processor device; and

accessing and executing instructions at the helper processor to perform at least one task on behalf of at least the external processor device.

18. The method of claim 17, further comprising:

operating the memory interface to perform a memory access for the helper processor device.

19. The method of claim 17, wherein accessing the instructions comprises accessing the instructions from at least one of:

a non-volatile memory of the IC package; and

the memory cell circuitry.

20. The method of claim 19, further comprising:

receiving, at the IC package, at least a portion of the instructions from the external processor device; and

storing the at least a portion of the instructions at the memory cell circuitry.

21. The method of claim 17, wherein:

the external processor device signals a request for an operation on a data structure stored in the memory cell circuitry;

accessing and executing instructions at the helper processor to perform the at least one task comprises accessing and executing instructions at the helper processor to perform the operation on the data structure stored in the memory cell circuitry; and

the method further comprises providing a result of the operation for output to the external processor device.

22. The method of claim 17, wherein:

accessing and executing instructions at the helper processor to perform the at least one task comprises accessing and executing instructions at the helper processor to perform an interrupt handling routine in response to an interrupt.

23. The method of claim 17, wherein accessing and executing instructions at the helper processor to perform the at least one task comprises accessing and executing instructions at the helper processor to execute at least one thread.

24. The system of claim 23, wherein the at least one thread includes at least one of:

a background operating system task;

a security scan task;

a virus scan task;

a defragmentation task;

a garbage collection task; and

a hypervisor task.

25. The method of claim 17, wherein:

the external processor device comprises a first external processor device; and

accessing and executing instructions at the helper processor to perform the at least one task comprises accessing and executing instructions at the helper processor to store at the memory cell circuitry a value representing a result of a computation performed by a second external processor device and to access the value from the memory cell circuitry and output the value to the first external processor device in response to a request from the first external processor device for the result of the computation from the second external processor device.

26. The method of claim 17, wherein

the external processor device comprises a first external processor device;

and

accessing and executing instructions at the helper processor to perform the at least one task comprises accessing and executing instructions at the helper processor to recalculate a result of a computation performed by a second external processor device by accessing data used in the computation from the memory cell circuitry, to perform the computation using the accessed data, and to output the result of the performed computation to a second external processor device in response to a request from the first second external processor device for the result of the computation from the second external processor.

27. A method comprising:

in response to a request from a processor device external to an integrated circuit (IC), executing instructions at a helper processor of the IC, the instructions including instructions to perform one or more data accesses to a stacked memory in communication with the helper processor.

28. The method of claim 27, further comprising:

providing a result from execution of the instructions from the IC to the external processor device.

29. The method of claim 27, further comprising:

accessing, in preparation for execution, the instructions from at least one of;

the stacked memory; and

a non-volatile memory.

30. The method of claim 27, wherein:

the request includes a thread identifier; and

executing the instructions at the helper processor comprises executing the thread at the helper processor in response to the thread identifier.

31. A method comprising:

executing instructions at helper processor of an integrated circuit (IC) package to perform an operation on a data structure stored in stacked memory of the IC package in response to a request from a processor device external to the IC package.

32. The method of claim 31, further comprising:

providing a result of the operation from the IC package to the processor device.

33. The method of claim 31, further comprising:

accessing, in preparation for execution, the instructions from at least one of;

the stacked memory; and

a non-volatile memory of the IC package.

34. The method of claim 31, wherein the operation comprises at least one of:

a search operation;

an insert operation;

a modify operation;

a delete operation;

a sort operation;

a find maximum operation;

a find minimum operation;

a find average, median, or mode operation;

a filtering operation;

a matrix operations;

a table join operation;

a MapReduce operation;

a fast Fourier transforms (FFTs) operation;

a graphic rendering operation; and

an audio processing operation.

35. An integrated circuit (IC) comprising:

a set of one or more logic layers electrically coupleable to a set of stacked memory layers implementing memory cell circuitry and electrically coupleable to a processor device external to the set of one or more logic layers, the set of one or more logic layers comprising a helper processor to execute instructions that utilize data stored in the memory cell circuitry on behalf of the external processor device.

36. The IC of claim 35, wherein the helper processor is to execute instructions stored in the memory cell circuitry.

37. The IC of claim 35, wherein the set of one or more logic layers further comprises:

a memory interface coupled to the helper processor and coupleable to the processor device, the memory interface to perform memory accesses for the external processor device and to perform memory accesses for the helper processor