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STACKED MEMORY DEVICE WITH HELPER PROCESSOR

  • US 20140040532A1
  • Filed: 08/06/2012
  • Published: 02/06/2014
  • Est. Priority Date: 08/06/2012
  • Status: Abandoned Application
First Claim
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1. A system comprising:

  • an integrated circuit (IC) package comprising;

    a set of stacked memory layers comprising memory cell circuitry; and

    a set of one or more logic layers electrically coupled to the set of stacked memory layers, the set of one or more logic layers comprising a helper processor coupled to the memory cell circuitry of the set of stacked memory layers and comprising a memory interface coupled to the helper processor and coupleable to a processor device external to the IC package, the memory interface to perform memory accesses for the external processor device and to perform memory accesses for the helper processor.

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