REWIND ONLY TRANSACTIONS IN A DATA PROCESSING SYSTEM SUPPORTING TRANSACTIONAL STORAGE ACCESSES

• US 20140040551A1
• Filed: 10/12/2012
• Published: 02/06/2014
• Est. Priority Date: 08/02/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: FREY, BRADLY G., GUTHRIE, GUY L., MAY, CATHY, WILLIAMS, DEREK E., BLAINEY, ROBERT J.
• Granted Patent: US 9,396,115 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

In a multiprocessor data processing system having a distributed shared memory system, a memory transaction that is a rewind-only transaction (ROT) and that includes one or more transactional memory access instructions and a transactional abort instruction is executed. In response to execution of the one or more transactional memory access instructions, one or more memory accesses to the distributed shared memory system indicated by the one or more transactional memory access instructions are performed. In response to execution of the transactional abort instruction, execution results of the one or more transaction memory access instructions are discarded and control is passed to a fail handler.

Claims

1. A method, comprising:

in a multiprocessor data processing system having a distributed shared memory system, executing a memory transaction that is a rewind-only transaction (ROT) including one or more transactional memory access instructions and a transactional abort instruction;

in response to execution of the one or more transactional memory access instructions, performing one or more memory accesses to the distributed shared memory system indicated by the one or more transactional memory access instructions; and

in response to execution of the transactional abort instruction, discarding execution results of the one or more transaction memory access instructions and passing control to a fail handler.

2. The method of claim 1, wherein:

the rewind-only transaction (ROT) includes bypass instructions; and

the method further includes in response to execution of the bypass instructions, determining whether the ROT should be aborted and, in response to determining the ROT should not be aborted, causing execution of the ROT to bypass execution of the transactional abort instruction.

3. The method of claim 1, wherein:

the rewind-only transaction (ROT) is a first memory transaction;

the method further comprises;

executing a second memory transaction that is a non-rewind-only transaction and, while executing the second memory transaction, tracking conflicts between both load and store footprints of the second memory transaction and memory accesses not within the second memory transaction; and

during execution of the rewind-only transaction (ROT), refraining from tracking conflicts between a load footprint of the ROT and memory accesses not within the ROT.

4. The method of claim 3, and further comprising:

during execution of the rewind-only transaction (ROT), tracking conflicts between a store footprint of the ROT and memory accesses not within the ROT.

5. The method of claim 4, and further comprising:

committing the rewind-only transaction (ROT) in response to bypassing execution of the transactional abort instruction and in response to detecting no conflict between the store footprint of the ROT and memory accesses not within the ROT.

6. The method of claim 5, wherein the committing further includes committing the rewind-only transaction (ROT) only in response to an invalidation necessitated by a memory update of a transactional store instruction among the transactional memory access instructions having fully propagated throughout the distributed shared memory system.

7. The method of claim 5, and further comprising:

in response to detecting a conflict between the store footprint of the rewind-only transaction (ROT) and a memory access not within the ROT, refraining from committing the ROT to the distributed shared memory system.

8. A data processing system, comprising:

a distributed shared memory system; and

a plurality of processor cores coupled to the distributed shared memory system, wherein a processor core among the plurality of processor cores executes a memory transaction that is a rewind-only transaction (ROT) including one or more transactional memory access instructions and a transactional abort instruction, initiates one or more memory accesses to the distributed shared memory system indicated by the one or more transactional memory access instructions in response to execution of the one or more transactional memory access instructions, and, responsive to execution of the transactional abort instruction, discards execution results of the one or more transaction memory access instructions and passes control to a fail handler.

9. The data processing system of claim 8, wherein:

the rewind-only transaction (ROT) includes bypass instructions; and

the processor core, responsive to execution of the bypass instructions, determines whether the ROT should be aborted and, responsive to determining the ROT should not be aborted, causes execution of the ROT to bypass execution of the transactional abort instruction.

10. The data processing system of claim 8, wherein:

the rewind-only transaction (ROT) is a first memory transaction;

the one or more processor cores execute a second memory transaction that is a non-rewind-only transaction; and

the distributed shared memory system includes transaction memory logic that, while executing the second memory transaction, tracks conflicts between both load and store footprints of the memory transaction and memory accesses not within the second memory transaction and that, during execution of the rewind-only transaction (ROT), refrains from tracking conflicts between a load footprint of the ROT and memory accesses not within the ROT.

11. The data processing system of claim 10, wherein the transaction memory logic, during execution of the rewind-only transaction (ROT), tracks conflicts between a store footprint of the ROT and memory accesses not within the ROT.

12. The data processing system of claim 11, wherein the distributed shared memory system commits the rewind-only transaction (ROT) in response to execution of the transactional abort instruction being bypassed and in response to the transactional memory logic detecting no conflict between the store footprint of the ROT and memory accesses not within the ROT.

13. The data processing system of claim 12, wherein the distributed shared memory system commits the memory transaction only in response to an invalidation necessitated by a memory update of a transactional store instruction among the transactional memory access instructions having fully propagated throughout the distributed shared memory system.

14. The data processing system of claim 12, wherein the distributed shared memory system, responsive to the transactional memory logic detecting a conflict between the store footprint of the rewind-only transaction (ROT) and a memory access not within the ROT, refrains from committing the ROT to the distributed shared memory system.

15. A processing unit for a multiprocessor data processing system, the processing unit comprising:

a multilevel cache hierarchy configured to form a portion of a distributed shared memory system in the multiprocessor data processing system; and

a processor core coupled to the multilevel cache hierarchy, wherein the processor core cores executes a memory transaction that is a rewind-only transaction (ROT) including one or more transactional memory access instructions and a transactional abort instruction, initiates one or more memory accesses to the distributed shared memory system indicated by the one or more transactional memory access instructions in response to execution of the one or more transactional memory access instructions, and, responsive to execution of the transactional abort instruction, discards execution results of the one or more transaction memory access instructions and passes control to a fail handler.

16. The processing unit of claim 15, wherein:

the rewind-only transaction (ROT) includes bypass instructions; and

the processor core, responsive to execution of the bypass instructions, determines whether the ROT should be aborted and, responsive to determining the ROT should not be aborted, causes execution of the ROT to bypass execution of the transactional abort instruction.

17. The processing unit of claim 15, wherein:

the rewind-only transaction (ROT) is a first memory transaction;

the multiprocessor data processing system executes a second memory transaction that is a non-rewind-only transaction; and

the processing unit includes transaction memory logic that, while executing the memory transaction, tracks conflicts between both load and store footprints of the memory transaction and memory accesses not within the memory transaction and that, during execution of the rewind-only transaction (ROT), refrains from tracking conflicts between a load footprint of the ROT and memory accesses not within the ROT.

18. The processing unit of claim 17, wherein the transaction memory logic, during execution of the rewind-only transaction (ROT), tracks conflicts between a store footprint of the ROT and memory accesses not within the ROT.

19. The processing unit of claim 18, wherein the multilevel cache hierarchy commits the rewind-only transaction (ROT) in response to execution of the transactional abort instruction being bypassed and in response to the transactional memory logic detecting no conflict between the store footprint of the ROT and memory accesses not within the ROT.

20. The processing unit of claim 19, wherein the multilevel cache hierarchy commits the memory transaction only in response to an invalidation necessitated by a memory update of a transactional store instruction among the transactional memory access instructions having fully propagated throughout the distributed shared memory system.

21. The processing unit of claim 19, wherein the multilevel cache hierarchy, responsive to the transactional memory logic detecting a conflict between the store footprint of the rewind-only transaction (ROT) and a memory access not within the ROT, refrains from committing the ROT to the distributed shared memory system.

22. A design structure tangibly embodied in a machine-readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a processing unit for a multiprocessor data processing system, the processing unit including;

a multilevel cache hierarchy configured to form a portion of a distributed shared memory system in the multiprocessor data processing system; and

a processor core coupled to the multilevel cache hierarchy, wherein the processor core cores executes a memory transaction that is a rewind-only transaction (ROT) including one or more transactional memory access instructions and a transactional abort instruction, initiates one or more memory accesses to the distributed shared memory system indicated by the one or more transactional memory access instructions in response to execution of the one or more transactional memory access instructions, and, responsive to execution of the transactional abort instruction, discards execution results of the one or more transaction memory access instructions and passes control to a fail handler.

23. The design structure of claim 22, wherein the design structure comprises a hardware description language (HDL) design structure.

24. A program product, comprising:

a computer-readable storage medium; and

program code stored within the computer-readable storage medium and executable by a data processing system having a shared memory system, the program code including;

executable instructions defining a rewind-only transaction (ROT) including;

one or more transactional memory access instructions that cause the data processing system to perform one or more speculative memory accesses to the shared memory system; and

a transactional abort instruction that causes the data processing system to discard execution results of the one or more transaction memory access instructions and pass control to a fail handler.