DEVICE BASED WEAR LEVELING

• US 20140040681A1
• Filed: 08/02/2012
• Published: 02/06/2014
• Est. Priority Date: 08/02/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Lee, Dana, Hsu, Jonathan, Wolfman, Jonathan
• Granted Patent: US 9,430,322 B2
• Time in Patent Office: Days
• US Class Current: 714/704
• CPC Class Codes: G01R 31/3171 BER [Bit Error Rate] test
• CPC Class Codes: G06F 11/07 Responding to the occurrence of a fault, e.g. fault tolerance
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/30 Monitoring
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/16 Protection against loss of memory contents contains no material, see G06F11/00
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: H04L 1/0061 Error detection codes

Abstract

A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage.

Claims

1. A flash memory device comprising:

a non-volatile storage having an array of memory blocks; and

a controller in communication with the non-volatile storage, wherein the controller is configured to;

estimate an intrinsic endurance for the memory blocks individually; and

adjust usage patterns of the memory blocks based on the individual intrinsic endurance of the memory blocks.

2. The device of claim 1 wherein to estimate the intrinsic endurance, the controller is configured to:

measure cell voltage distribution; and

assign the intrinsic endurance based on the measured cell voltage distribution.

3. The device of claim 1 wherein to estimate the intrinsic endurance, the controller is configured to:

measure a number of failed bits; and

assign the intrinsic endurance based on the number of failed bits.

4. The device of claim 3 wherein the number of failed bits is measured with enhanced post-write read, bit error rate, or failed bit count.

5. The device of claim 1 wherein estimation and adjustment are performed during usage of the device.

6. The device of claim 1 wherein the adjustment of the usage patterns further comprises:

programming the memory blocks with a lower estimated endurance with a lower voltage.

7. The device of claim 1 wherein the adjustment of usage further comprises retiring the memory blocks with a lowest estimated endurance.

8. The device of claim 1 wherein the adjustment of the usage patterns further comprises:

measuring a hot count for individual blocks of erase operations that reflects actual usage of those blocks; and

offsetting the hot count based on the estimated endurance.

9. The device of claim 8 wherein the hot count is reduced for those blocks with a high estimated endurance and the hot count is increased for those blocks with a low estimated endurance.

10. The device of claim 1 wherein the adjustment of usage further comprises:

receiving requests for host operations, wherein host operations that require less data retention are assigned to the memory blocks with lower estimated intrinsic endurance.

11. The device of claim 1 wherein the adjustment of usage further comprises:

assigning blocks with lower estimated intrinsic endurance to data with additional data backup protections, wherein the additional data backup protections comprises RAID or backup copies.

12. The device of claim 1 wherein the adjustment of usage further comprises:

assigning the blocks based on a host application that utilizes the blocks, wherein lower intrinsic endurance blocks are utilized for host applications that require less data retention.

13. A method for block level grading in flash memory comprising:

in a non-volatile storage device having a controller and blocks of memory, the controller;

estimating an intrinsic endurance of the blocks of memory based on physical characteristics during usage of the non-volatile storage device; and

adjusting programming of the non-volatile storage device based on the estimated intrinsic endurance.

14. The method of claim 13 wherein the physical characteristics during usage comprises a cell voltage distribution, wherein the estimating the intrinsic endurance is based on the cell voltage distribution.

15. The method of claim 14 wherein the cell voltage distribution is measured after an operation where wordlines in a block are written together.

16. The method of claim 13 wherein the physical characteristics during usage comprises a number of failed bits, wherein the estimating the intrinsic endurance is based on the number of failed bits.

17. The method of claim 16 wherein the number of failed bits is measured with enhanced post-write read, bit error rate, or failed bit count.

18. The method of claim 13 wherein the programming adjustment comprises programming the memory blocks with a lower estimated endurance with a lower voltage.

19. A memory system comprising:

a non-volatile storage having an array of memory blocks; and

a controller in communication with the blocks, the controller configured to;

predict an intrinsic endurance for the blocks; and

modify the storing of data to one of the memory blocks based on the predicted intrinsic endurance of that memory block.

20. The memory system of claim 19 wherein the prediction is based on measurements of the blocks during usage and wherein the measurements are based on physical characteristics of the blocks including cell voltage distribution or a number of failed bits.