STACKED MEMORY DEVICE WITH METADATA MANGEMENT

• US 20140040698A1
• Filed: 08/06/2012
• Published: 02/06/2014
• Est. Priority Date: 08/06/2012
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Loh, Gabriel H., O'Connor, James M., Beckmann, Bradford M., Ignatowski, Michael
• Granted Patent: US 9,697,147 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager'"'"'s tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.

Claims

1. An integrated circuit (IC) package comprising:

memory cell circuitry; and

a set of one or more logic layers electrically coupled to the memory cell circuitry, the set of one or more logic layers comprising a metadata manager and a memory interface, the memory interface coupled to the metadata manager and coupleable to a device external to the IC package, and the metadata manager to manage metadata stored at the IC package and which is associated with operational data stored at the memory cell circuitry for the device.

2. The IC package of claim 1, further comprising a set of stacked memory layers implementing the memory cell circuitry.

3. The IC package of claim 2, wherein the metadata manager is to perform at least one metadata management operation in response to a memory access request from the device.

4. The IC package of claim 3, wherein:

the metadata comprises a memory utilization metric associated with a specified memory address range; and

the at least one metadata management operation comprises updating the memory utilization metric responsive to a match between the specified memory address range and a memory address identified by the memory access request.

5. The IC package of claim 3, wherein:

the metadata comprises memory log information; and

the at least one metadata management operation comprises updating the memory log information with a memory address identified by the memory access request.

6. The IC package of claim 3, wherein:

the metadata comprises an error detection value associated with operational data stored at a memory address that is identified by the memory access request, the error detection value comprising at least one of a parity value, a checksum, and an error correcting code; and

the at least one metadata management operation comprises at least one of computing or validating the error detection value using the operational data stored at the memory address.

7. The IC package of claim 2, wherein the metadata manager is to perform at least one metadata management operation in response to a metadata command from the device.

8. The IC package of claim 7, wherein:

the metadata comprises address translation information; and

the at least one metadata management operation comprises accessing the address translation information to translate the virtual address to the physical address.

9. The IC package of claim 7, wherein:

the metadata comprises memory utilization profiling information; and

the at least one metadata management operation comprises at least one of;

configuring at least one parameter of a memory utilization profiling operation to be performed by the metadata manager;

resetting at least one profiling metric of the memory utilization profiling information; and

accessing the memory utilization profiling information for output to the device.

10. The IC package of claim 7, wherein:

the metadata comprises memory log information; and

the at least one metadata management operation comprises at least one of;

configuring at least one parameter of a memory logging operation to be performed by the metadata manager; and

accessing the memory log information for output to the device.

11. The IC package of claim 7, wherein:

the metadata comprises garbage collection attributes; and

the at least one metadata management operation comprises modifying at least one of the garbage collection attributes.

12. The IC package of claim 2, wherein:

the metadata is stored at the memory cell circuitry; and

the memory interface is to access the metadata from the memory cell circuitry and provide the accessed metadata to the device in response to a request from the device.

13. The IC package of claim 12, wherein:

the metadata manager is to provide to the device a memory address of the memory cell circuitry at which the metadata is stored; and

the request includes the memory address.

14. The IC package of claim 2, wherein the metadata is stored in at least one storage element in the set of one or more logic layers.

15. The IC package of claim 2, wherein the metadata manager is to perform at least one metadata management operation independent of signaling from the device.

16. The IC package of claim 2, wherein the set of stacked memory layers and the set of one or more logic layers are disposed in a stacked configuration whereby the memory interface is connected to the stacked memory layers via a set of through silicon vias.

17. The IC package of claim 2, wherein the set of stacked memory layers and the set of one or more logic layers are disposed in a side-split arrangement whereby memory interface is connected to the stacked memory layers via an interposer.

18. A computer readable medium storing code to adapt at least one computer system to perform a portion of a process to fabricate at least part of the IC package of claim 1.

19. A method comprising:

providing an integrated circuit (IC) comprising a set of stacked memory layers comprising memory cell circuitry and comprising a set of one or more logic layers electrically coupled to the set of stacked memory layers, the set of one or more logic layers comprising a metadata manager coupled to the memory cell circuitry of the set of one or more stacked memory layers and comprising a memory interface coupled to the metadata manager and coupled to a device external to the IC;

operating the memory interface to perform memory accesses for the device; and

the metadata manager managing metadata stored at the IC.

20. The method of claim 19, wherein the IC comprises a set of stacked memory layers implementing the memory cell circuitry.

21. The method of claim 20, wherein managing metadata comprises performing at least one metadata management operation in response to a memory access request from the device.

22. The method of claim 21, wherein the at least one metadata management operation comprises at least one of:

updating a memory utilization metric stored at the IC responsive to a match between a specified memory address range and a memory address identified by the memory access request;

updating memory log information stored at the IC with a memory address identified by a memory access request; and

at least one of computing and validating an error detection value associated with operational data stored at a memory address identified by the memory access request, the error detection value comprising at least one of a parity value, a checksum, and an error correcting code.

23. The method of claim 20, wherein managing metadata comprises performing at least one metadata management operation in response to a metadata command from the device.

24. The method of claim 22, wherein the at least one metadata management operation comprises at least one of:

accessing address translation information stored at the IC to translate a virtual address identified by the metadata command to a physical address;

configuring at least one parameter of a memory utilization profiling operation to be performed by the metadata manager;

resetting at least one profile metric of a memory utilization profiling operation to be performed by the metadata manager;

configuring at least one parameter of a memory logging operation to be performed by the metadata manager;

accessing memory log information stored at the IC for output to the device; and

modifying at least one garbage collection attribute associated with the operational data.

25. The method of claim 20, wherein the metadata is stored at the memory cell circuitry, and the method further comprises:

accessing the metadata from the memory cell circuitry and providing the accessed metadata to the device.

26. The method of claim 20, wherein the metadata is stored in at least one storage element in the set of one or more logic layers, and the method further comprises:

accessing the metadata from the at least one storage element and providing the accessed metadata to the device.

27. A system comprising:

a stacked memory device comprising;

a set of stacked memory layers comprising memory cell circuitry; and

a set of one or more logic layers electrically coupled to the set of stacked memory layers, the set of one or more logic layers comprising a metadata manager and a memory interface, the metadata manager to manage metadata stored at the stacked memory device; and

a processor device coupled to the stacked memory device via the memory interface, the processor device to provide operational data for storage at the set of stacked memory and to issue a metadata command to the stacked memory device to initiate a performance of at least one metadata management operation by the metadata manager for metadata associated with the operational data.

28. The system of claim 27, wherein the metadata is stored at the memory cell circuitry.

29. The system of claim 27, wherein the metadata is stored in at least one storage element in the set of one or more logic layers.

30. An integrated circuit (IC) comprising:

a set of one or more logic layers electrically coupleable to memory cell circuitry, the set of one or more logic layers comprising a metadata manager and a memory interface, the memory interface coupled to the metadata manager and coupleable to a device external to the IC, and the metadata manager to manage metadata stored at the IC and which is associated with operational data stored at the memory cell circuitry for the device.

31. The IC of claim 30, further comprising:

a set of stacked memory layers implementing the memory cell circuitry.

32. The IC of claim 31, wherein the metadata manager is to perform at least one metadata management operation in response to a memory access request from the device.

33. The IC of claim 31, wherein the metadata manager is to perform at least one metadata management operation in response to a metadata command from the device.

34. The IC of claim 31, wherein the metadata manager is to perform at least one metadata management operation independent of signaling from the device.

35. A processor comprising:

a memory interface coupleable to an integrated circuit device having memory cell circuitry and one or more logic layers comprising a metadata manager; and

wherein the processor is to store operational data at the integrated circuit device and to direct the metadata manager to manage metadata associated with the stored operational data.

36. The processor of claim 35, wherein the processor is to provide a metadata command to the integrated circuit device, the metadata command to direct the metadata manager to perform at least one metadata management operation.

37. A system comprising:

a processor; and

integrated circuit (IC) separate from the processor, the IC comprising;

memory cell circuitry;

a memory interface coupled to the memory cell circuitry and coupled to the processor; and

a metadata manager coupled to memory interface, the metadata manager to manage metadata stored at the IC and which is associated with operational data stored at the memory cell circuitry for the processor.

38. The system of claim 37, wherein the metadata manager is to perform at least one metadata management operation in response to a memory access request from the device.

39. The system of claim 37, wherein the metadata manager is to perform at least one metadata management operation in response to a metadata command from the device.

40. The system of claim 37, wherein the metadata manager is to perform at least one metadata management operation independent of signaling from the device.