FIELD EFFECT TRANSISTOR DEVICE

• US 20140042455A1
• Filed: 08/08/2013
• Published: 02/13/2014
• Est. Priority Date: 08/09/2012
• Status: Active Grant

• Current Assignee: Ancora Semiconductors Incorporated, Delta Electronics Incorporated, National Central University
• Original Assignee: Delta Electronics Incorporated, National Central University
• Inventors: CHEN, Shih-Peng, CHYI, Jen-Inn, LIN, Hui-Ling, LEE, Geng-Yen
• Granted Patent: US 9,093,510 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

A field effect transistor device is provided by the invention. The field effect transistor device includes: a substrate; a buffer layer, a channel layer, and a first barrier layer sequentially disposed on the substrate; a two-dimensional electron gas controlling layer disposed on the first barrier layer; a second barrier layer disposed on the two-dimensional electron gas controlling layer, wherein the second barrier layer has a recess passing through the second barrier layer; and a gate electrode filled into the recess and separated from the second barrier layer and the two-dimensional electron gas controlling layer by an insulating layer.

Claims

1. A field effect transistor device, comprising:

a substrate;

a buffer layer, a channel layer, and a first barrier layer sequentially disposed on the substrate;

a two-dimensional electron gas controlling layer disposed on the first barrier layer, wherein the two-dimensional electron gas controlling layer has a thickness of more than or equal to 5 nm;

a second barrier layer disposed on the two-dimensional electron gas controlling layer, wherein the second barrier layer has a recess passing through the second barrier layer; and

a gate electrode filled into the recess and separated from the second barrier layer and the two-dimensional electron gas controlling layer by an insulating layer.

2. The field effect transistor device as claimed in claim 1, further comprising:

a source electrode and a drain electrode disposed to be spaced apart from each other on the second barrier layer.

3. The field effect transistor device as claimed in claim 1, wherein the channel layer is made of Al_xGa_(1-x)N, and x is of between 0-0.5.

4. The field effect transistor device as claimed in claim 3, wherein the first barrier layer is made of Al_yGa_(1-y)N, and y is of between 0.05-0.5, wherein y is larger than x.

5. The field effect transistor device as claimed in claim 4, wherein the two-dimensional electron gas controlling layer is made of Al_zGa_(1-x)N, z is of between 0-0.5, wherein y is larger than z.

6. The field effect transistor device as claimed in claim 1, wherein the second barrier layer comprises AlInN.

7. The field effect transistor device as claimed in claim 1, wherein the second barrier layer is made of Al_hIn_(1-h)N, and h is of between 0.8-1.

8. The field effect transistor device as claimed in claim 7, wherein the recess exposes a top surface of the two-dimensional electron gas controlling layer.

9. The field effect transistor device as claimed in claim 1, further comprising a cap layer disposed on the second barrier layer.

10. The field effect transistor device as claimed in claim 1, wherein the recess passes through the second barrier layer and a part of the two-dimensional electron gas controlling layer, and a minimum distance between a bottom surface of the recess and a bottom surface of the two-dimensional electron gas controlling layer is larger than or equal to 5 nm.

11. The field effect transistor device as claimed in claim 1, wherein the channel layer has a first two-dimensional electron gas concentration and the two-dimensional electron gas controlling layer has a second two-dimensional electron gas concentration, wherein the second two-dimensional electron gas concentration is larger than the first two-dimensional electron gas concentration.

12. The field effect transistor device as claimed in claim 1, wherein the field effect transistor device is capable of operating as a normally-off switch.

13. The field effect transistor device as claimed in claim 1, wherein the second barrier layer has an energy gap larger than the channel layer.

14. The field effect transistor device as claimed in claim 1, wherein the field effect transistor device has a mobility of larger than 800 cm²/Vs.

15. The field effect transistor device as claimed in claim 1, further comprising:

an AlN layer disposed between the two-dimensional electron gas controlling layer and the second barrier layer.

16. A method of manufacturing a field effect transistor device, comprising:

providing a substrate;

sequentially forming a buffer layer, a channel layer, and a first barrier layer sequentially on the substrate;

forming a two-dimensional electron gas controlling layer on the first barrier layer, wherein the two-dimensional electron gas controlling layer has a thickness of more than or equal to 5 nm;

forming a second barrier layer on the two-dimensional electron gas controlling layer;

patterning the second barrier layer to form a recess passing through the second barrier layer; and

forming an insulating layer to cover sidewalls and a bottom surface of the recess, and filling a gate electrode into the recess.

17. The method as claimed in claim 16, wherein the method for patterning the second barrier layer comprises dry etching.

18. The method as claimed in claim 16, wherein the recess passes through the second barrier layer and a part of the two-dimensional electron gas controlling layer, and a minimum distance between a bottom surface of the recess and a bottom surface of the two-dimensional electron gas controlling layer is larger than or equal to 5 nm.

19. The method as claimed in claim 16, wherein the method for patterning the second barrier layer comprises wet etching.

20. A field effect transistor device, comprising:

a substrate;

a channel layer disposed on the substrate;

a first barrier layer disposed on the channel layer, the first barrier layer having a larger band gap than the channel layer;

a two-dimensional electron gas controlling layer disposed on the first barrier layer;

a second barrier layer disposed on the two-dimensional electron gas controlling layer, wherein the second barrier layer comprises AlInN and has a recess passing through the second barrier layer; and

a gate electrode filled disposed in the recess;

wherein the two-dimensional electron gas controlling layer has enough thickness to prevent to two-dimensional electron gases to be generated at the channel layer under the gate electrode.