TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS

• US 20140042532A1
• Filed: 10/21/2013
• Published: 02/13/2014
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Challa, Ashok, Kinzer, Daniel M., Probst, Dean E., Calafut, Daniel
• Granted Patent: US 8,963,212 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Claims

1. A semiconductor device, comprising:

at least a first device area and a second device area disposed at a surface of a semiconductor region, the second device area being adjacent to the first device area and spaced apart from the first device area;

a connection region disposed between the first and second device areas;

a first trench extending into the semiconductor region and at least extending from the first device region, through the connection region, and to the second device region;

a first dielectric layer lining opposing sidewalls of the first trench;

a first electrode disposed in the first trench; and

a first conductive trace disposed over the first trench in the connection region and electrically coupled to the first electrode in the connection region.

2. The semiconductor device of claim 1, wherein the first electrode comprises a gate electrode, and has a dielectric disposed over it in each of the device regions.

3. The semiconductor device of claim 1, wherein the first electrode comprises a shield electrode, and wherein the semiconductor device further comprises a gate electrode disposed in the first trench but electrically insulated from the shield electrode.

4. The semiconductor device of claim 3, further comprising a second conductive trace disposed over the first trench in the connection region and electrically coupled to the gate electrode in the connection region, and electrically insulated from the shield electrode.

5. The semiconductor device of claim 1, further comprising a first mesa disposed adjacent to the first trench, a first configuration of one or more material bodies with a portion of the first mesa region within the connection region, a second configuration of one or more material bodies with the portion of the first mesa region within the first device region, a third configuration of one or more material bodies with the portion of the first mesa region within second first device region, wherein the first configuration is different from each of the second and third configurations.

6. The semiconductor device of claim 1, further comprising

a second trench extending into the semiconductor region and at least extending from the first device region, through the connection region, and to the second device region;

a second dielectric layer lining opposing sidewalls of the second trench;

a second electrode disposed in the second trench; and

a well region of a first conductivity type disposed in the semiconductor region and between the first and second trenches, the well region having a first end; and

a second conductive trace disposed over the first and second trenches, the conductive trace having a length running perpendicular to the trenches and a width that is less than the length, the second conductive trace having a portion spaced from a portion of the semiconductor region disposed between the trenches by a first distance, the portion of the second trace having a first and second sides parallel to the length of the trace, the first side being closer to the first end of the well region than the second side; and

wherein the first end of the well region is spaced from the second side of the second conductive trace by at least a second distance.

7. The semiconductor device of claim 6, wherein the well region is electrically coupled to a conductive layer to receive a potential.

8. The semiconductor device of claim 6, wherein the well region extends a first depth into the semiconductor region, and wherein the second distance is equal to the first depth.

9. The semiconductor device of claim 6, wherein the well region extends a first depth into the semiconductor region, and wherein the second distance is equal to the first distance plus the first depth.

10. The semiconductor device of claim 6, further comprising a second well region of a first conductivity type disposed in the semiconductor region, between the first and second trenches, and under the first conductive trace.

11. The semiconductor device of claim 10, wherein the second well region is electrically floating.

12. The semiconductor device of claim 1, further comprising a well region of a first conductivity type disposed in the semiconductor region and under the first conductive trace.

13. The semiconductor device of claim 12, wherein the well region is electrically floating.

14. The semiconductor device of claim 1, further comprising:

a second trench extending into the semiconductor region and at least extending from the first device region, through the connection region, and to the second device region;

a second dielectric layer lining opposing sidewalls of the second trench;

a second electrode disposed in the second trench; and

a well region of a first conductivity type disposed in the semiconductor region and between the first and second trenches, the well region extending from the first device region, through the connection region, and to the second device region.

15. A semiconductor device, comprising:

a plurality of trenches extending into a semiconductor region, each of the plurality of trenches having a first end, a second end, and opposing sidewalls lined with a dielectric layer, each trench further having a shield electrode and a gate electrode vertically stacked on the shield electrode, the gate and shield electrodes being insulated from each other; and

a conductive shield trace disposed over the semiconductor region and having a length running adjacent to the first ends of the trenches and a width that does not extend over the ends of the first trenches, the conductive shield trace making electrical contact to the shield electrodes.

16. A semiconductor device, comprising:

a plurality of trenches extending into a semiconductor region, each of the plurality of trenches having a first end, a second end, and opposing sidewalls lined with a dielectric layer, each trench further having a shield electrode; and

a conductive shield trace disposed over the semiconductor region and having a length running adjacent to the first ends of the trenches and a width extending over the ends of the first trenches, the conductive shield trace making electrical contact to the shield electrodes.

17. The semiconductor device of either claim 16, wherein the semiconductor device comprises a trench-shield Shottky barrier diode.