METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING GRINDING FROM A BACK SURFACE AND SEMICONDUCTOR DEVICE

• US 20140042595A1
• Filed: 08/10/2012
• Published: 02/13/2014
• Est. Priority Date: 08/10/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Schulze, Hans-Joachim, Mauder, Anton
• Granted Patent: US 8,772,126 B2
• Time in Patent Office: Days
• US Class Current: 257/622
• CPC Class Codes: B24B 37/013 Devices or means for detecting lapping completion
• CPC Class Codes: B24B 37/042 operating processes therefor
• CPC Class Codes: B24B 7/228 for grinding thin, brittle parts, e.g. semiconductors, wafers grinding edges of thin, brittle parts B24B9/065
• CPC Class Codes: H01L 21/302 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors

Abstract

A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device.

Claims

1. A method of manufacturing a semiconductor device, the method comprising etching a cavity from a front surface into a semiconductor substrate;

providing an etch stop structure from at least one of silicon oxide, silicon nitride and silicon oxynitride at the bottom of the cavity;

closing the cavity;

grinding the semiconductor substrate from a back surface opposite to the front surface at least up to an edge of the etch stop structure oriented toward the back surface;

monitoring, during grinding, a grind stop signal indicating exposure of the etch stop structure; and

stopping or controlling the grinding in response to detection of the grind stop signal.

2. The method according to claim 1, wherein

the cavity is closed in a portion adjoining the front surface.

3. The method according to claim 2, wherein

a void is left in a portion of the cavity.

4. The method according to claim 1, wherein

the cavity widens with increasing distance from the front surface.

5. The method according to claim 4, wherein

providing the etch stop structure and closing the cavity comprise providing an etch stop layer lining an inner surface of the cavity, the etch stop layer closing the cavity at the front surface and leaving a void in the cavity.

6. The method according to claim 4, wherein

the cavity forms a circumferential trench surrounding a mesa portion of the semiconductor device at a distance to an outer surface of a semiconductor body of the semiconductor device, and further comprising

forming semiconductor elements in the mesa portion.

7. The method according to claim 4, wherein

providing the etch stop layer comprises annealing a semiconductor material of the semiconductor substrate in an oxygen containing ambient to convert a portion of the semiconductor material into a semiconductor oxide forming at least a portion of the etch stop layer.

8. The method according to claim 7, wherein

a plurality of the cavities is etched along a circumferential line surrounding a mesa portion of a semiconductor body of the semiconductor device at a distance to an outer surface of the semiconductor body, neighboring cavities being separated by fins of the semiconductor material, the fins being converted to semiconductor oxide during the tempering in the oxygen containing ambient.

9. The method according to claim 1, wherein

the cavity forms a grid in the semiconductor substrate, and the method further comprises

forming semiconductor elements in meshes of the grid;

and

singularizing a semiconductor die of the semiconductor device from the semiconductor substrate along a parting line through the cavity.

10. The method according to claim 1, wherein

providing the etch stop structure comprises providing an etch resistive material at the bottom of the cavity, the etch resistive material being absent in a portion of the cavity above the etch stop structure.

11. The method according to claim 10, wherein

closing the cavity comprises tempering, after providing the etch stop structures, the semiconductor substrate in a hydrogen containing ambient to control a collapse of the cavity above the etch stop structure and to form a contiguous layer of a semiconductor material forming the semiconductor substrate above the collapsed cavity, the etch stop structure forming a buried etch stop island.

12. The method according to claim 11, further comprising

planarizing the contiguous layer.

13. The method according to claim 11, further comprising

forming a semiconductor element in the contiguous layer of the semiconductor material in a vertical direction above the buried etch stop island.

14. The method according to claim 11, further comprising removing the buried etch stop island.

15. A semiconductor device comprising

a semiconductor body;

a trench structure extending from a front surface into the semiconductor body, the trench structure comprising an etch stop layer lining an inner surface of the trench structure and surrounding a void within the trench structure.

16. The semiconductor device according to claim 15, wherein

the trench structure extends to a back surface opposite to the front surface of the semiconductor body.

17. The semiconductor device according to claim 15, wherein

the trench structure widens with increasing distance from the front surface.

18. The semiconductor device according to claim 15, wherein

the trench structure is a circumferential trench structure surrounding a mesa portion of the semiconductor body at a distance to an outer surface tilted to the front surface.

19. The semiconductor device according to claim 15, wherein

a plurality of cavities is arranged along a circumferential line surrounding a mesa portion of the semiconductor body at a distance to an outer surface tilted to the front surface, neighboring cavities being separated by fins of a semiconductor oxide.

20. The semiconductor device according to claim 15, wherein

the trench structure is a circumferential edge structure surrounding the semiconductor body along an outer surface of the semiconductor body.

21. A semiconductor substrate comprising

a disc-shaped semiconductor corpus;

a trench structure forming a grid extending from a front surface into the semiconductor corpus, the trench structure comprising an etch stop layer that lines an inner surface of the trench structure and leaves a space within the trench structure.

22. The semiconductor substrate according to claim 21, wherein

the trench structure widens with increasing distance from the front surface.

23. The semiconductor substrate according to claim 21, wherein

the trench structure is closed on the front surface.

24. A semiconductor device comprising

a semiconductor body in which a plurality of electrically separated doped zones are formed along a front surface;

a plurality of buried etch stop islands formed in the semiconductor body and directly adjoining a back surface of the semiconductor body opposite to the front surface in a vertical projection of the doped zones perpendicular to the front surface.

25. A method of manufacturing a semiconductor device, the method comprising

etching a cavity forming a grid from a front surface into a semiconductor substrate;

providing an etch stop structure from at least one of silicon oxide, silicon nitride and silicon oxynitride at the bottom of the cavity;

closing the cavity at least partially;

grinding the semiconductor substrate from a back surface opposite to the front surface at least up to an edge of the etch stop structure oriented to the back surface;

monitoring, during grinding, a grind stop signal indicating exposure of the etch stop structure;

stopping or controlling the grinding in response to detection of the grind stop signal; and

singularizing a semiconductor die from the semiconductor substrate along a parting line cutting through the etch stop structure.

26. The method according to claim 25, wherein

the cavity is completely filled.