METHOD FOR PACKAGING CIRCUITS
First Claim
1. A chip-scale-packaging method, comprising:
- singulating dice from a first wafer;
testing the singulated dice;
forming final I/O locations on a second wafer;
applying adhesive to a top surface of the second wafer;
placing a singulated die on the adhesive over the final I/O locations;
removing a back surface of the second wafer to expose the final I/O locations; and
connecting the singulated die to an electric circuit through the final I/O location.
8 Assignments
0 Petitions
Accused Products
Abstract
A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.
4 Citations
20 Claims
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1. A chip-scale-packaging method, comprising:
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singulating dice from a first wafer; testing the singulated dice; forming final I/O locations on a second wafer; applying adhesive to a top surface of the second wafer; placing a singulated die on the adhesive over the final I/O locations; removing a back surface of the second wafer to expose the final I/O locations; and connecting the singulated die to an electric circuit through the final I/O location. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method, comprising:
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providing a plurality of integrated circuit dice; providing a substrate having electrical signal terminals thereon with at least two of the electrical signal terminals being interconnected; fixing a first die on the substrate over a first group of the electrical signal terminals; fixing a second die on the substrate over a second group of the electrical signal terminals; forming electrical connections from first die to first group of electrical signal terminals; forming electrical connections from second die to second group of electrical signal terminals; removing a backside of substrate to expose the terminals; and separating the first and second dice from a remainder of the substrate with the first and second dice being adapted to electrically communicate through at least the interconnected electrical signal terminals. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A method of forming an integrated circuit (IC) package component, comprising:
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fabricating a non-conductive base substrate having electrical conductors vertically extending from a top surface of the base substrate into the substrate and terminating within the base substrate, the top surface of the base substrate includes an interconnect area sized to receive an IC die; and removing a portion of a bottom surface of the base substrate to expose the electrical conductors such that the electrical conductors are exposed on both the top and bottom surfaces of the base substrate. - View Dependent Claims (19, 20)
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Specification