INTERACTION OF TRANSACTIONAL STORAGE ACCESSES WITH OTHER ATOMIC SEMANTICS

• US 20140047205A1
• Filed: 10/12/2012
• Published: 02/13/2014
• Est. Priority Date: 08/10/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: FREY, BRADLY G., GUTHRIE, GUY L., MAY, CATHY, WILLIAMS, DEREK E.
• Granted Patent: US 9,430,166 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 3/0668 adopting a particular infrastructure
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

In a processor, an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block is detected. In response to detecting the instruction sequence, the processor causes the conditional write access to the target memory block to fail.

Claims

1. A method of data processing in a data processing system, the method comprising:

in a processor, detecting an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block; and

in response to detecting the instruction sequence, the processor causing the conditional write access to the target memory block to fail.

2. The method of claim 1, wherein the instruction delimiting transactional memory access instructions belonging to the memory transaction is an instruction that initiates the memory transaction.

3. The method of claim 2, wherein:

the method further comprises the processor detecting an instruction terminating the memory transaction; and

the processor core causing the conditional write access to the target memory block to fail comprises the processor core causing the conditional write access to the target memory block to fail unless the processor detects the instruction terminating the memory transaction within the instruction sequence after the instruction initiating the memory transaction and prior to the store-conditional instruction.

4. The method of claim 1, wherein:

the instruction delimiting transactional memory access instructions belonging to the memory transaction is an instruction that delimits a suspended region within the memory transaction in which memory accesses are performed regardless of whether the memory transaction commits successfully; and

the method further comprises the processor core performing a memory access indicated by a memory access instruction within the suspended region of the memory transaction regardless of whether the memory transaction commits successfully.

5. The method of claim 4, wherein:

the instruction comprises an instruction initiating the suspended region;

the method further comprises the processor detecting an instruction terminating the suspended region; and

the processor core causing the conditional write access to the target memory block to fail comprises the processor core causing the conditional write access to the target memory block to fail unless the processor detects the instruction terminating the suspended region within the instruction sequence after the instruction initiating the suspended region and prior to the store-conditional instruction.

6. The method of claim 4, wherein:

the instruction comprises an instruction initiating the suspended region;

the method further comprises;

setting a fail flag to indicate that the conditional write access should fail in response to detecting the instruction initiating the suspended region;

resetting the fail flag in response to detecting another load-and-reserve instruction within the suspended region; and

the processor core causing the conditional write access to the target memory block to fail comprises the processor core causing the conditional write access to the target memory block to fail only in response to the fail flag being set.

7. The method of claim 1, wherein the instruction delimiting transactional memory access instructions belonging to the memory transaction is an instruction that terminates the memory transaction.

8. The method of claim 1, wherein:

the method further comprises setting a reservation flag to indicate a valid reservation in response to execution of the load-and-reserve instruction; and

the processor core causing the conditional write access to the target memory block to fail includes resetting the reservation flag.

9. A processing unit, comprising:

at least one execution unit that executes an instruction sequence; and

logic that detects in the instruction sequence, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block, and responsive to detecting the instruction sequence, causing the conditional write access to the target memory block to fail.

10. The processing unit of claim 9, wherein the instruction delimiting transactional memory access instructions belonging to the memory transaction is an instruction that initiates the memory transaction.

11. The processing unit of claim 10, wherein the logic causes the conditional write access to the target memory block to fail unless the processor detects an instruction terminating the memory transaction within the instruction sequence after the instruction initiating the memory transaction and prior to the store-conditional instruction.

12. The processing unit of claim 9, wherein the instruction delimiting transactional memory access instructions belonging to the memory transaction is an instruction that delimits a suspended region within the memory transaction in which memory accesses are performed regardless of whether the memory transaction commits successfully.

13. The processing unit of claim 12, wherein:

the instruction comprises an instruction initiating the suspended region;

the logic causes the conditional write access to the target memory block to fail unless the processor detects an instruction terminating the suspended region within the instruction sequence after the instruction initiating the suspended region and prior to the store-conditional instruction.

14. The processing unit of claim 12, wherein:

the instruction comprises an instruction initiating the suspended region;

the processing unit further includes a fail flag;

the logic, in response to detecting the instruction initiating the suspended region, sets the fail flag to indicate that the conditional write access should fail and, in response to detecting another load-and-reserve instruction within the suspended region, resets the fail flag; and

the logic causing the conditional write access to the target memory block to fail only in response to the fail flag being set.

15. The processing unit of claim 9, wherein the instruction delimiting transactional memory access instructions belonging to the memory transaction is an instruction that terminates the memory transaction.

16. The processing unit of claim 9, wherein:

the processing unit further includes a reservation flag;

the logic sets the reservation flag to indicate a valid reservation in response to execution of the load-and-reserve instruction; and

logic causes the conditional write access to the target memory block to fail by resetting the reservation flag.

17. A data processing system, comprising:

a plurality of processing units in accordance with claim 9; and

an interconnect fabric coupling the plurality of processing units.

18. A design structure tangibly embodied in a machine-readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a processing unit, including;

at least one execution unit that executes an instruction sequence; and

logic that detects in the instruction sequence, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block, and responsive to detecting the instruction sequence, causing the conditional write access to the target memory block to fail.

19. The design structure of claim 18, wherein the instruction delimiting transactional memory access instructions belonging to the memory transaction is an instruction that initiates the memory transaction.

20. The design structure of claim 19, wherein the logic causes the conditional write access to the target memory block to fail unless the processor detects an instruction terminating the memory transaction within the instruction sequence after the instruction initiating the memory transaction and prior to the store-conditional instruction.

21. The design structure of claim 18, wherein the instruction delimiting transactional memory access instructions belonging to the memory transaction is an instruction that delimits a suspended region within the memory transaction in which memory accesses are performed regardless of whether the memory transaction commits successfully.

22. The design structure of claim 21, wherein:

the instruction comprises an instruction initiating the suspended region;

the logic causes the conditional write access to the target memory block to fail unless the processor detects an instruction terminating the suspended region within the instruction sequence after the instruction initiating the suspended region and prior to the store-conditional instruction.

23. The design structure of claim 21, wherein:

the instruction comprises an instruction initiating the suspended region;

the processing unit further includes a fail flag;

the logic, in response to detecting the instruction initiating the suspended region, sets the fail flag to indicate that the conditional write access should fail and, in response to detecting another load-and-reserve instruction within the suspended region, resets the fail flag; and

the logic causing the conditional write access to the target memory block to fail only in response to the fail flag being set.

24. The design structure of claim 18, wherein the instruction delimiting transactional memory access instructions belonging to the memory transaction is an instruction that terminates the memory transaction.

25. The design structure of claim 18, wherein:

the processing unit further includes a reservation flag;

the logic sets the reservation flag to indicate a valid reservation in response to execution of the load-and-reserve instruction; and

logic causes the conditional write access to the target memory block to fail by resetting the reservation flag.

26. The design structure of claim 18, wherein the design structure comprises a hardware description language (HDL) design structure.