Microprocessor Unit Capable of Multiple Power Modes

• US 20140047247A1
• Filed: 05/03/2010
• Published: 02/13/2014
• Est. Priority Date: 05/04/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Rzehak, Volker, Diewald, Horst
• Granted Patent: US 9,092,206 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A power mode control system for microprocessors offers an unlimited variety of hardware-supported power modes that may satisfy any operating scenario. The microprocessor unit comprises a register that contains particular bit fields for defining selectable power modes. The particular bit fields in the register define pointers to a power mode defining register. Each pointer selects a corresponding bit field in the power mode defining register. The bits in the bit fields of the power mode defining register either directly control a power mode of at least one functional or peripheral blocks of the unit; or they are pointers to a further power mode defining register and the bits in the bit fields of the further power mode defining register directly control a power mode of at least one functional or peripheral blocks of the unit.

Claims

1. A microprocessor unit capable of multiple power modes, comprising:

at least one register containing bit fields defining selectable power modes, wherein

a first set of bit fields directly controls at least one power modes, and

a second set of bit fields define pointers to at least one power mode defining register, each pointer selecting a corresponding bit field in the power mode defining register.

2. The microprocessor unit according to claim 1, wherein:

at least some of the particular bit fields in the register directly controls a power mode of at least one functional block of the microprocessor unit.

3. The microprocessor unit according to claim 1, wherein:

the bits in the bit fields of the power mode defining register directly control a power mode of at least one functional block of the microprocessor unit.

4. The microprocessor unit according claim 1, wherein:

the bits in the bit fields of the power mode defining register are pointers to a further power mode defining register and the bits in the bit fields of the further power mode defining register directly control a power mode of at least one functional block of the microprocessor unit.

5. The microprocessor unit according claim 1, wherein:

said register holding the particular bit fields is an existing register of the unit such as a status register, a CPU register and a memory area.

6. The microprocessor unit according claim 1, wherein:

said register holding the particular bit fields is responsive to control events.

12. The method according to claim 1, wherein:

the contents of power mode control bit fields are protected and changes are subject to the occurrence of particular events.

13. The method according to claim 1, wherein:

the contents of power mode control bit fields are protected and changes are subject to specific authorization.

7. A method of operating a microprocessor unit, comprising the steps of:

accepting control events;

saving the contents of a power mode defining register when a control event is accepted;

executing the control event; and

restoring the contents of the power mode defining register after execution of the control event.

8. The method according to claim 7, wherein:

an accepted event contains an index to a bit field of the power mode defining register.

9. The method according to claim 7, wherein:

the contents of power mode control bit fields are defined by hardware.

10. The method according to claim 7, wherein:

the contents of power mode control bit fields are defined by software.

11. The method according to claim 7, wherein;

the contents of power mode control bit fields are open to change in accordance with user requirements.