OPERATING METHOD FOR MEMORY SYSTEM INCLUDING NONVOLATILE RAM AND NAND FLASH MEMORY

• US 20140047269A1
• Filed: 08/07/2013
• Published: 02/13/2014
• Est. Priority Date: 08/07/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, BOGEUN
• Granted Patent: US 9,223,656 B2
• Time in Patent Office: Days
• US Class Current: 714/16
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

An operating method for a memory system including a nonvolatile random access memory (NVRAM) and a NAND flash memory includes; performing a normal read operation directed to the target memory cell in response to a read request, determining that a read fail has occurred as a result of the normal read operation, then performing a read retry operation by iterations directed to the target memory cell according to a first read retry scheme until a pass read retry iteration successfully reads the target memory cell, and storing pass information associated with the pass read retry iteration in the NVRAM.

Claims

1. An operating method for a memory system including a nonvolatile random access memory (NVRAM) and a NAND flash memory, the method comprising:

receiving a read request directed to a target memory cell of the NAND flash memory;

performing a normal read operation directed to the target memory cell in response to the read request; and

then,

determining that a read fail has occurred as a result of the normal read operation; and

then in response to the read fail,

performing a read retry operation by iterations directed to the target memory cell according to a first read retry scheme until a pass read retry iteration successfully reads the target memory cell; and

then,

storing pass information associated with the pass read retry iteration in the NVRAM.

2. The operating method of claim 1, further comprising:

further in response to the read fail and before performing the read retry operation by iterations directed to the target memory cell, reading pass information related to the read request previously stored in the NVRAM, wherein the first read retry scheme is defined at least in part by the pass information read from the NVRAM.

3. The operating method of claim 2, further comprising:

determining whether a number of program/erase (P/E) cycles for the target memory cell has reached a reference value; and

upon determining that the number of P/E cycles for the target memory cell has not reached the reference value, performing the read retry operation by iterations directed to the target memory cell according to a second read retry scheme different from the first read retry scheme until a pass read retry iteration successfully reads the target memory cell, instead of reading the pass information related to the read request previously stored from the NVRAM and performing the read retry operation by iterations directed to the target memory cell according to the first read retry scheme until the pass read retry iteration successfully reads the target memory cell.

4. The operating method of claim 2, wherein the pass information comprises information related to at least one level for a read voltage used during the read retry operation as defined by the first read retry scheme.

5. The operating method of claim 4, wherein the pass information further comprises at least one bit error rate for the read retry operation as iteratively performed using the at least one level of the read voltage.

6. The operating method of claim 4, wherein the pass information comprises a number of P/E cycles for the target memory cell once the pass read retry iteration successfully reads the target memory cell.

7. The operating method of claim 3, wherein the pass information comprises information related to at least one level for a read voltage used during the read retry operation as defined by the second read retry scheme.

8. The operating method of claim 7, wherein the pass information further comprises at least one bit error rate for the read retry operation as iteratively performed using the at least one level of the read voltage.

9. The operating method of claim 7, wherein the pass information comprises a number of P/E cycles for the target memory cell once the pass read retry iteration successfully reads the target memory cell.

10. The operating method of claim 1, wherein the pass information comprises information characterizing a minima valley existing between adjacent, overlapping threshold voltage distributions for the target memory cell.

11. An operating method for a memory system including a nonvolatile random access memory (NVRAM) and a NAND flash memory, the method comprising:

receiving a read request directed to a target memory cell of the NAND flash memory;

determining whether a number of program/erase (P/E) cycles for the target memory cell has reached a reference value; and

(A) upon determining that the number of P/E cycles for the target memory cell has not reached the reference value, performing a first normal read operation with default voltages directed to the target memory cell;

else

(B) upon determining that the number of P/E cycles for the target memory cell has reached the reference value, reading pass information related to the read request previously stored in the NVRAM, and performing a second normal read operation with adjusted voltages by read pass information directed to the target memory cell; and

then,

determining that a read fail has occurred as a result of the first or second normal read operation; and

then in response to the read fail,

performing a read retry operation by iterations directed to the target memory cell until a pass read retry iteration successfully reads the target memory cell; and

then,

storing updated pass information associated with the pass read retry iteration in the NVRAM.

12. The operating method of claim 11, wherein the pass information comprises information related to at least one level for a read voltage used during the read retry operation.

13. The operating method of claim 12, wherein the pass information further comprises at least one bit error rate for the read retry operation as iteratively performed using the at least one level of the read voltage.

14. The operating method of claim 12, wherein the pass information comprises a number of P/E cycles for the target memory cell once the pass read retry iteration successfully reads the target memory cell.

15. An operating method for a memory system including a nonvolatile random access memory (NVRAM) and a NAND flash memory, the method comprising:

receiving a read request directed to a target memory cell of the NAND flash memory;

performing a normal read operation directed to the target memory cell in response to the read request; and

then,

determining that a read fail has occurred as a result of the normal read operation; and

then in response to the read fail,

iteratively performing an read operation using different read voltages to obtain pass information;

making a soft decision regarding the programmed state of the target memory cell in relation to the pass information; and

storing the pass information in the NVRAM.

16. The operating method of claim 15, further comprising:

further in response to the read fail and before performing iteratively performing the read operation, reading pass information related to the read request previously stored in the NVRAM.

17. The operating method of claim 16, wherein the read operation is defined at least in part by the pass information read from the NVRAM.

18. The operating method of claim 15, wherein the pass information comprises information related to the different read voltages used during the read operation.

19. The operating method of claim 18, wherein the pass information further comprises at least one bit error rate for the read operation.

20. The operating method of claim 18, wherein the pass information comprises a number of P/E cycles for the target memory cell once the soft decision has been made.