Utilizing A Kernel Administration Hardware Thread Of A Multi-Threaded, Multi-Core Compute Node Of A Parallel Computer

• US 20140047450A1
• Filed: 08/08/2012
• Published: 02/13/2014
• Est. Priority Date: 08/08/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Blocksome, Michael A., Inglett, Todd A., McCarthy, Patrick J., Ratterman, Joseph D., Smith, Brian E.
• Granted Patent: US 8,930,956 B2
• Time in Patent Office: Days
• US Class Current: 718/104
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

Methods, apparatuses, and computer program products for utilizing a kernel administration hardware thread of a multi-threaded, multi-core compute node of a parallel computer are provided. Embodiments include a kernel assigning a memory space of a hardware thread of an application processing core to a kernel administration hardware thread of a kernel processing core. A kernel administration hardware thread is configured to advance the hardware thread to a next memory space associated with the hardware thread in response to the assignment of the kernel administration hardware thread to the memory space of the hardware thread. Embodiments also include the kernel administration hardware thread executing an instruction within the assigned memory space.

Claims

1. A method of utilizing a kernel administration hardware thread of a multi-threaded, multi-core compute node of a parallel computer, the compute node comprising a kernel processing core and a plurality of parallel application processing cores, the kernel processing core comprising a plurality of kernel administration hardware threads, each application processing core comprising a plurality of hardware threads, the method comprising:

assigning to the kernel administration hardware thread, by a kernel executing on the kernel processing core, a memory space of a hardware thread of one of the application processing cores;

in response to the assignment of the kernel administration hardware thread to the memory space of the hardware thread, advancing, by the kernel administration hardware thread, the hardware thread to a next memory space associated with the hardware thread; and

executing, by the kernel administration hardware thread, an instruction within the assigned memory space.

2. The method of claim 1 further comprising:

in response to the kernel administration hardware thread completing execution of the instruction within the assigned memory space, selecting, by the kernel, a memory space of another hardware thread of the plurality of application processing cores to assign to the kernel administration hardware thread; and

assigning to the kernel administration hardware thread, by the kernel, the selected memory space.

3. The method of claim 2, wherein selecting, by the kernel, a memory space of another hardware thread to assign to the kernel administration hardware thread is carried out asynchronously, in a predetermined order of the hardware threads of the plurality of application processing cores.

4. The method of claim 1, wherein the kernel processing core comprises:

at least one kernel administration hardware thread dedicated to executing the kernel; and

a plurality of kernel administration hardware threads that are available for executing instructions within memory spaces associated with the hardware threads of the plurality of application processing cores.

5. The method of claim 4, wherein each of the kernel administration hardware threads is concurrently assigned by the kernel to a memory space of a different application processing core.

6. The method of claim 1, wherein the hardware thread of the one of the application processing cores is advanced without advancing code corresponding to an instruction that the one of the application processing cores is currently executing.

7. An apparatus for utilizing a kernel administration hardware thread of a multi-threaded, multi-core compute node of a parallel computer, the compute node comprising a kernel processing core and a plurality of parallel application processing cores, the kernel processing core comprising a plurality of kernel administration hardware threads, each application processing core comprising a plurality of hardware threads, the apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that when executed by the computer processor cause the apparatus to carry out the steps of:

assigning to the kernel administration hardware thread, by a kernel executing on the kernel processing core, a memory space of a hardware thread of one of the application processing cores;

in response to the assignment of the kernel administration hardware thread to the memory space of the hardware thread, advancing, by the kernel administration hardware thread, the hardware thread to a next memory space associated with the hardware thread; and

executing, by the kernel administration hardware thread, an instruction within the assigned memory space.

8. The apparatus of claim 7 further comprising computer program instructions that when executed by the computer processor cause the apparatus to carry out the steps of:

in response to the kernel administration hardware thread completing execution of the instruction within the assigned memory space, selecting, by the kernel, a memory space of another hardware thread of the plurality of application processing cores to assign to the kernel administration hardware thread; and

assigning to the kernel administration hardware thread, by the kernel, the selected memory space.

9. The apparatus of claim 8, wherein selecting, by the kernel, a memory space of another hardware thread of the plurality of application processing cores to assign to the kernel administration hardware thread is carried out asynchronously, in a predetermined order of the hardware threads of the plurality of application processing cores.

10. The apparatus of claim 7, wherein the kernel processing core comprises:

at least one kernel administration hardware thread dedicated to executing the kernel; and

a plurality of kernel administration hardware threads that are available for executing instructions within memory spaces associated with the hardware threads of the plurality of application processing cores.

11. The apparatus of claim 10, wherein each of the kernel administration hardware threads is concurrently assigned by the kernel to a memory space of a different application processing core.

12. The apparatus of claim 7, wherein the hardware thread of the one of the application processing cores is advanced without advancing code corresponding to an instruction that the one of the application processing cores is currently executing.

13. A computer program product for utilizing a kernel administration hardware thread of a multi-threaded, multi-core compute node of a parallel computer, the compute node comprising a kernel processing core and a plurality of parallel application processing cores, the kernel processing core comprising a plurality of kernel administration hardware threads, each application processing core comprising a plurality of hardware threads, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that when executed cause a computer to carry out the steps of:

assigning to the kernel administration hardware thread, by a kernel executing on the kernel processing core, a memory space of a hardware thread of one of the application processing cores;

in response to the assignment of the kernel administration hardware thread to the memory space of the hardware thread, advancing, by the kernel administration hardware thread, the hardware thread to a next memory space associated with the hardware thread; and

executing, by the kernel administration hardware thread, an instruction within the assigned memory space.

14. The computer program product of claim 13 further comprising computer program instructions that when executed cause a computer to carry out the steps of:

in response to the kernel administration hardware thread completing execution of the instruction within the assigned memory space, selecting, by the kernel, a memory space of another hardware thread of the plurality of application processing cores to assign to the kernel administration hardware thread; and

assigning to the kernel administration hardware thread, by the kernel, the selected memory space.

15. The computer program product of claim 14, wherein selecting, by the kernel, a memory space of another hardware thread of the plurality of application processing cores to assign to the kernel administration hardware thread is carried out asynchronously, in a predetermined order of the hardware threads of the plurality of application processing cores.

16. The computer program product of claim 13, wherein the kernel processing core comprises:

at least one kernel administration hardware thread dedicated to executing the kernel; and

a plurality of kernel administration hardware threads that are available for executing instructions within memory spaces associated with the hardware threads of the plurality of application processing cores.

17. The computer program product of claim 16, wherein the hardware thread of the one of the application processing cores is advanced without advancing code corresponding to an instruction that the one of the application processing cores is currently executing.

18. The computer program product of claim 13, wherein the memory space of the hardware thread of the one of the application processing cores is advanced without advancing code that the one of the application processing cores is currently executing.

19. The computer program product of claim 13, wherein the computer readable medium is a signal bearing medium.

20. The computer program product of claim 13, wherein the computer readable medium is a storage medium.