SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THE SAME

• US 20140048798A1
• Filed: 08/19/2013
• Published: 02/20/2014
• Est. Priority Date: 07/10/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, OHARA, Hiroki, SAKATA, Junichiro, SASAKI, Toshinari, HOSOBA, Miyuki
• Granted Patent: US 9,269,794 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 27/1296 adapted to increase the uniformity of device parameters
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced.

Claims

1. (canceled)

2. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating layer over the gate electrode layer;

a connection electrode layer over the gate insulating layer;

an oxide semiconductor layer over the gate insulating layer;

a source electrode layer over the oxide semiconductor layer;

an insulating film over the source electrode layer;

a gate wiring over the insulating film; and

a source wiring over the insulating film, the source wiring overlapping with the connection electrode layer,

wherein the gate wiring is electrically connected to the gate electrode layer and the connection electrode layer,

wherein the source wiring is electrically connected to the source electrode layer, and

wherein the oxide semiconductor layer comprises a nanocrystal grain.

3. The semiconductor device according to claim 2, wherein each of the gate wiring and the source wiring comprises a conductive material which has lower resistivity than the source electrode layer.

4. The semiconductor device according to claim 2, wherein each of the gate wiring and the source wiring comprises at least one of aluminum and copper.

5. The semiconductor device according to claim 2, wherein the source electrode layer and the connection electrode layer are formed from the same layer.

6. The semiconductor device according to claim 2, wherein the gate electrode layer, the connection electrode layer and the source electrode layer are formed using a single layer or a stacked layer of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component.

7. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating layer over the gate electrode layer;

a connection electrode layer over the gate insulating layer;

an oxide semiconductor layer over the gate insulating layer;

a source electrode layer over the oxide semiconductor layer;

an insulating film over the source electrode layer;

a gate wiring over the insulating film; and

a source wiring over the insulating film, the source wiring overlapping with the connection electrode layer,

wherein the gate wiring is electrically connected to the gate electrode layer and the connection electrode layer,

wherein the source wiring is electrically connected to the source electrode layer, and

wherein the oxide semiconductor layer comprises a crystal grain having a diameter of 1 nm to 10 nm.

8. The semiconductor device according to claim 7, wherein each of the gate wiring and the source wiring comprises a conductive material which has lower resistivity than the source electrode layer.

9. The semiconductor device according to claim 7, wherein each of the gate wiring and the source wiring comprises at least one of aluminum and copper.

10. The semiconductor device according to claim 7, wherein the source electrode layer and the connection electrode layer are formed from the same layer.

11. The semiconductor device according to claim 7, wherein the gate electrode layer, the connection electrode layer and the source electrode layer are formed using a single layer or a stacked layer of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component.

12. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating layer over the gate electrode layer;

a connection electrode layer over the gate insulating layer;

an oxide semiconductor layer over the gate insulating layer;

an inorganic layer over the oxide semiconductor layer, the inorganic layer comprising oxygen;

a source electrode layer over the oxide semiconductor layer and the inorganic layer;

an insulating film over the source electrode layer;

a gate wiring over the insulating film; and

a source wiring over the insulating film, the source wiring overlapping with the connection electrode layer,

wherein the gate wiring is electrically connected to the gate electrode layer and the connection electrode layer,

wherein the source wiring is electrically connected to the source electrode layer, and

wherein the oxide semiconductor layer comprises a nanocrystal grain.

13. The semiconductor device according to claim 12, wherein the inorganic layer comprises a film selected from the group consisting of a silicon oxide film, a silicon oxynitride film and a silicon nitride oxide film.

14. The semiconductor device according to claim 12, further comprising a conductive layer over the insulating film,

wherein the conductive layer overlaps with the oxide semiconductor layer.

15. The semiconductor device according to claim 14, wherein a same potential is applied to the conductive layer and the gate electrode layer.

16. The semiconductor device according to claim 14, wherein the conductive layer is a part of the gate wiring.

17. The semiconductor device according to claim 12, wherein each of the gate wiring and the source wiring comprises a conductive material which has lower resistivity than the source electrode layer.

18. The semiconductor device according to claim 12, wherein each of the gate wiring and the source wiring comprises at least one of aluminum and copper.

19. The semiconductor device according to claim 12, wherein the source electrode layer and the connection electrode layer are formed from the same layer.

20. The semiconductor device according to claim 12, wherein the gate electrode layer, the connection electrode layer and the source electrode layer are formed using a single layer or a stacked layer of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component.