RING OSCILLATOR TIMER CIRCUIT

• US 20140049328A1
• Filed: 06/27/2013
• Published: 02/20/2014
• Est. Priority Date: 08/20/2012
• Status: Active Grant

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Smith, Patrick A., Knierim, Daniel G.
• Granted Patent: US 9,077,322 B2
• Time in Patent Office: Days
• US Class Current: 331/57
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/0322 with differential cells

Abstract

A ring oscillator timer circuit can include a plurality of electrical components arranged in a cascaded combination of delay stages connected in a closed loop chain. The timer circuit can begin oscillation a programmable number of gate delays after receiving a start signal. In some examples, the number of gate delays can be programmed to fractional values. In further examples, the ring oscillator timer circuit can include a counter having an input electrically coupled to an output of a reset component.

Claims

1. A phase-startable ring oscillator having an output at which is produced an oscillator signal, comprising:

a first input receiving a start control signal to control the onset of oscillation from a static state; and

a second input receiving control data that control the generation of a predetermined signal level at the output during the static state, and select an initial gate delay of the oscillator signal from a predetermined set of selectable initial gate delays;

wherein, in response to the start signal, the oscillator continues to generate the predetermined signal level at the output for the selected gate delay time, and begins oscillation thereafter.

2. The phase-startable ring oscillator of claim 1, further comprising at least one inverting stage.

3. The phase-startable ring oscillator of claim 2, further comprising an odd number of inverting stages.

4. The phase-startable ring oscillator of claim 1, further comprising a plurality of NAND gates.

5. The phase-startable ring oscillator of claim 1, further comprising a plurality of NOR gates.

6. The phase-startable ring oscillator of claim 1, further comprising a first plurality of multiplexers.

7. The phase-startable ring oscillator of claim 6, further comprising a second plurality of multiplexers coupled with the first plurality of multiplexers.

8. The phase-startable ring oscillator of claim 7, wherein the second plurality of multiplexers are fractional multiplexers and the gate delay time has a fractional value.

9. The phase-startable ring oscillator of claim 8, wherein the fractional multiplexers are configured to receive a digital-to-analog (DAC) signal.

10. The phase-startable ring oscillator of claim 8, wherein the fractional multiplexers are configured to receive information from a memory.

11. The phase-startable ring oscillator of claim 6, further comprising a plurality of digital-to-analog converters (DACs) coupled with the first plurality of multiplexers, wherein the gate delay time has a fractional value.

12. The phase-startable ring oscillator of claim 1, further comprising a counter receiving the oscillator signal.

13. The phase-startable ring oscillator of claim 12, wherein the control data further determine the state of the counter during the static state prior to onset of oscillation.

14. The phase-startable ring oscillator of claim 1 further comprising a third input receiving an injection clock signal.

15. The phase-startable ring oscillator of claim 14, further comprising a fourth input controlling the amplitude of the injection clock signal injected into the ring oscillator.