SEMICONDUCTOR APPARATUS

• US 20140050021A1
• Filed: 12/19/2012
• Published: 02/20/2014
• Est. Priority Date: 08/17/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Dong Keun
• Granted Patent: US 8,976,567 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A semiconductor apparatus includes: a first bank group comprising a plurality of first banks; a second bank group comprising a plurality of second banks arranged adjacent to the first bank group; a write operation controller arranged between the first and second bank groups so as to be adjacent to the first and second bank groups, and configured to control write operations of the first and second bank groups; and a read operation controller arranged adjacent to any one of the first and second bank groups and configured to control read operations of the first and second bank groups.

Claims

1. A semiconductor apparatus comprising:

a first bank group comprising a plurality of first banks;

a second bank group comprising a plurality of second banks arranged adjacent to the first bank group;

a write operation controller arranged between the first and second bank groups so as to be adjacent to the first and second bank groups, and configured to control write operations of the first and second bank groups; and

a read operation controller arranged adjacent to any one of the first and second bank groups and configured to control read operations of the first and second bank groups.

2. The semiconductor apparatus according to claim 1, further comprising:

a write global bit line connected to one or more bit lines arranged in each of the banks; and

a read global bit line connected to one or more bit lines arranged in each of the banks.

3. The semiconductor apparatus according to claim 1, wherein each of the first and second bank groups comprises:

a cell mat having a plurality of bit lines and word lines arranged therein;

a first write global bit line switch connected to write global bit lines arranged in the first bank group and configured to perform a switching operation;

a second write global bit line switch connected to write global bit lines arranged in the second bank group and configured to perform a switching operation;

a read global bit line switch connected to read global bit lines arranged in all of the plurality of banks and configured to perform a switching operation; and

a local bit line switch configured to select any one of the plurality of bit lines arranged in the cell mat, when data is transmitted from the write global bit line and the read global bit line.

4. The semiconductor apparatus according to claim 3, wherein the write operation controller is connected to the first and second write global bit line switches.

5. The semiconductor apparatus according to claim 4, wherein the write operation controller comprises:

a write driver connected to the first and second write global bit line switches and configured to output a write driving signal to a selected write global bit line; and

a verify sense amplifier connected to the first and second write global bit line switches and configured to receive written data from the selected write global bit line and verify whether a write operation is normally performed or not.

6. The semiconductor apparatus according to claim 3, wherein the read operation controller comprises a sense amplifier connected to the read global bit line switch and configured receive read data from a selected read global bit line and output the received data to the outside.

7. The semiconductor apparatus according to claim 1, wherein the semiconductor apparatus comprises a phase-change random access memory (PRAM).

8. The semiconductor apparatus according to claim 1, wherein the first bank group and second bank group are configured as a stacked bank structure.

9. The semiconductor apparatus according to claim 1, wherein:

the semiconductor apparatus comprises a core area and a peripheral area; and

the first bank group, second bank group, write operation controller, and read operation controller are all arranged within the core area.

10. The semiconductor apparatus according to claim 9, wherein the read operation controller is arranged substantially around the edge of the core area substantially adjacent to the peripheral area.

11. A semiconductor apparatus having a stacked structure of a plurality of banks, comprising:

one write driver and one sense amplifier connected to the plurality of banks; and

a verify sense amplifier connected to the write driver and configured to verify a write operation performed in any one bank selected among the plurality of banks.

12. The semiconductor apparatus according to claim 11, further comprising:

a plurality of write global bit lines connected to one or more bit lines arranged in the plurality of banks and configured to transmit write data during a write operation; and

a plurality of read global bit lines connected to one or more bit lines arranged in the plurality of banks and configured to transmit read data during a read operation.

13. The semiconductor apparatus according to claim 12, wherein the write driver and the verify sense amplifier are arranged among the plurality of banks.

14. The semiconductor apparatus according to claim 13, wherein the write driver is connected to the plurality of write global bit lines, and generates a write driving signal to transmit write data inputted from outside through any one write global bit line selected among the plurality of write global bit lines, when a write command is inputted from outside or a verification output signal is inputted from the verify sense amplifier.

15. The semiconductor apparatus according to claim 13, wherein the verify sense amplifier is connected to the plurality of write global bit lines, receives write data of a previously-performed write operation through any one write global bit line selected among the plurality of write global bit lines, verifies whether or not the received write data is input write data, and transmits a verification output signal to the write driver.

16. The semiconductor apparatus according to claim 12, wherein the sense amplifier is connected to the plurality of read global bit lines, receives read data through any one read global bit line selected among the plurality of read global bit lines when a read command is inputted from outside, amplifies the received read data, and outputs the amplified data to outside.

17. The semiconductor apparatus according to claim 13, further comprising:

a write global bit line switch arranged among the write driver, the verify sense amplifier, and the plurality of banks, and configured to select any one of the plurality of write global bit lines connected to the plurality of banks; and

a read global bit line switch arranged between the sense amplifier and the plurality of banks, and configured to select any one of the plurality of read global bit lines connected to the plurality of banks.

18. The semiconductor apparatus according to claim 11, wherein the semiconductor apparatus comprises a PRAM.

19. The semiconductor apparatus according to claim 11, wherein:

the semiconductor apparatus comprises a core area and a peripheral area; and

the plurality of banks, write driver, sense amplifier, and verify sense amplifier are all arranged within the core area.

20. The semiconductor apparatus according to claim 19, wherein the sense amplifier is arranged substantially around the edge of the core area substantially adjacent to the peripheral area.