METHOD FOR WAFER-LEVEL TESTING DICED MULTI-CHIP STACKED PACKAGES
First Claim
1. A method for wafer-level testing a plurality of diced multi-chip stacked packages, comprising the steps of:
- providing the plurality of multi-chip stacked packages where each multi-chip stacked package includes a plurality of chips vertically stacked together and has a top surface, a bottom surface, and a plurality of testing electrodes disposed on the top surface;
fixing the multi-chip stacked packages on a transparent reconstructed wafer according to a die-on-wafer array arrangement wherein the transparent reconstructed wafer includes a plurality of component placement regions defined by a plurality of alignment marks and has a photosensitive adhesive adhered to the bottom surfaces of the multi-chip stacked packages to locate the multi-chip stacked packages within the component placement regions, wherein the transparent reconstructed wafer further has a barcode of wafer ID disposed at an edge of the transparent reconstructed wafer outside the component placement regions;
loading the transparent reconstructed wafer with the multi-chip stacked packages into a wafer tester;
using a plurality of probes of a probe card installed in the wafer tester to probe the testing electrodes to electrically test the multi-chip stacked packages; and
radiating light on the photosensitive adhesive through the transparent reconstructed wafer to pick up and sort out the multi-chip stacked packages.
1 Assignment
0 Petitions
Accused Products
Abstract
Disclosed is a method for wafer-level testing a plurality of diced multi-chip stacked packages. Each package includes a plurality of chips with vertically electrical connections such as TSVs. Next, according to a die-on-wafer array arrangement, the multi-chip stacked packages are fixed on a transparent reconstructed wafer by a photo-sensitive adhesive, and the packages are located within the component-bonding area of the wafer. Then, the transparent reconstructed wafer carrying the multi-chip stacked packages can be loaded into a wafer tester for probing. Accordingly, the wafer testing probers in the wafer tester can be utilized to probe the testing electrodes of the stacked packages so that it is easy to integrate this wafer-level testing method especially into TSV packaging processes.
32 Citations
16 Claims
-
1. A method for wafer-level testing a plurality of diced multi-chip stacked packages, comprising the steps of:
-
providing the plurality of multi-chip stacked packages where each multi-chip stacked package includes a plurality of chips vertically stacked together and has a top surface, a bottom surface, and a plurality of testing electrodes disposed on the top surface; fixing the multi-chip stacked packages on a transparent reconstructed wafer according to a die-on-wafer array arrangement wherein the transparent reconstructed wafer includes a plurality of component placement regions defined by a plurality of alignment marks and has a photosensitive adhesive adhered to the bottom surfaces of the multi-chip stacked packages to locate the multi-chip stacked packages within the component placement regions, wherein the transparent reconstructed wafer further has a barcode of wafer ID disposed at an edge of the transparent reconstructed wafer outside the component placement regions; loading the transparent reconstructed wafer with the multi-chip stacked packages into a wafer tester; using a plurality of probes of a probe card installed in the wafer tester to probe the testing electrodes to electrically test the multi-chip stacked packages; and radiating light on the photosensitive adhesive through the transparent reconstructed wafer to pick up and sort out the multi-chip stacked packages. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. (canceled)
-
16. A method for wafer-level testing a plurality of diced multi-chip stacked packages, comprising the steps of:
-
providing the plurality of multi-chip stacked packages where each multi-chip stacked package includes a plurality of chips vertically stacked together and has a top surface, a bottom surface, and a plurality of testing electrodes disposed on the top surface; fixing the multi-chip stacked packages on a transparent reconstructed wafer according to a die-on-wafer array arrangement wherein the transparent reconstructed wafer includes a plurality of component placement regions defined by a plurality of alignment marks and has a photosensitive adhesive adhered to the bottom surfaces of the multi-chip stacked packages to locate the multi-chip stacked packages within the component placement regions, wherein the alignment marks include a plurality of central alignment marks corresponding to the component placement regions; loading the transparent reconstructed wafer with the multi-chip stacked packages into a wafer tester; using a plurality of probes of a probe card installed in the wafer tester to probe the testing electrodes to electrically test the multi-chip stacked packages; and radiating light on the photosensitive adhesive through the transparent reconstructed wafer to pick up and sort out the multi-chip stacked packages.
-
Specification