MEMORY ADDRESS TRANSLATION METHOD FOR FLASH STORAGE SYSTEM

• US 20140052899A1
• Filed: 08/18/2012
• Published: 02/20/2014
• Est. Priority Date: 08/18/2012
• Status: Abandoned Application

• Current Assignee: StorArt Technology (Shenzhen) Co., Ltd.
• Original Assignee: StorArt Technology (Shenzhen) Co., Ltd.
• Inventors: Nan, Yen Chih
• Application Number:
  US13/589,124
• Publication Number:
  US 20140052899A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A memory address translation method for flash storage system is disclosed. There are two level mapping tables to reduce overhead of mapping table management. In level-one mapping table, each entry contains two kinds of information, which one is the validation of this entry, called Valid Mark and the other is the location of level-two mapping. The level-one mapping table is always located on RAM, and never saved into flash memory. In level-two mapping table, each entry contains two kinds of information, which one is the validation of this entry and the other is the physical location of data in flash memory. The physical addresses of both data and level-two mapping table are dynamically determined. Level-two mapping table is loaded to RAM when it is needed to reference, and is saved into flash memory periodically if the content is updated.

Claims

1. A memory address translation method for flash storage system, which the flash memory storage system has a RAM including a level-one mapping and a flash memory including a level-two mapping table, the steps comprising:

saving at least one first entry with two information in the level-one mapping table storing in the RAM, one information of the first entry is a validation of the first entry, and the other information of the first entry is a location of level-two mapping; and

saving at least one second entry with two information in the level-two mapping table storing in the flash memory, one information of the second entry is a validation of the second entry, and the other information of the second entry is a physical location of data in flash memory.

2. The method as claimed in claim 1, wherein the level-one mapping is dynamic rebuilt at the storage system powered on a initialization stage.

3. The method as claimed in claim 1, wherein the physical location information is different between each second entry in the level-two mapping table.

4. The method as claimed in claim 1, wherein a size of the data that level-two mapping table maps to is a byte, a word, a double word, a sector, a physical page, multiple physical pages, a physical block, or multiple physical blocks.

5. The method as claimed in claim 1, wherein the physical addresses of both the data and the level-two mapping table are dynamically determined.

6. The method as claimed in claim 1, wherein the level-two mapping table is loaded to the RAM when it is needed to reference, and is saved into the flash memory periodically if a content of the level-two mapping table is updated.