RANDOM ACCESS OF A CACHE PORTION USING AN ACCESS MODULE

• US 20140052922A1
• Filed: 11/30/2012
• Published: 02/20/2014
• Est. Priority Date: 08/20/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C., Scott, Jeffrey W.
• Granted Patent: US 9,448,942 B2
• Time in Patent Office: Days
• US Class Current: 711/128
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.

Claims

1. A method comprising:

identifying during operation of an integrated circuit a first portion of a cache memory for servicing access requests from a random access generator, and identifying a second portion of the cache memory that cannot service access requests from the random access generator;

executing a security sensitive operation at a processor core that includes the cache memory; and

in response to being identified, using the first portion of the cache memory to service access requests generated by the random access generator during execution of the security sensitive operation.

2. The method of claim 1, wherein the processor core is an instruction-based processor core of an integrated circuit die having a single processor core.

3. The method of claim 1, wherein the processor core is a first core of an integrated circuit die having multiple instruction-based processor cores.

4. The method of claim 3, wherein the cache memory is dedicated to the first core.

5. The method of claim 1, wherein the random access generator is implemented with built-in self-test hardware that includes a random number generator to provide random number to randomize a characteristic of the access requests.

6. The method of claim 1, wherein executing the security sensitive operation includes executing a fetched instruction at an execution unit of the processor core, and further includes storing at the second portion of the cache memory at least one of the fetched instruction and operand data of the security sensitive operation.

7. The method of claim 6, wherein, in response to being identified, the first portion of the cache is not available to service access requests of the execution unit.

8. The method of claim 1, wherein identifying the first portion of the cache comprises reading an enable indicator from a user programmable location.

9. The method of claim 8, wherein the enable indicator is one of a plurality of valid indicators, each valid indicator identifying one or more ways of the cache as the first portion, including a first indicator that identifies the first portion to be exactly one way of a cache, and a second indicator that identifies the first portion to be two or more ways of the cache.

10. The method of claim 1, wherein the first portion is a first way of a plurality of ways of the cache memory.

11. The method of claim 1, wherein servicing the access requests during execution of the security sensitive operation includes servicing the access requests and executing of the security sensitive operation occurring concurrently.

12. The method of claim 1 wherein the service access request generated by the random access generator includes a write access request that is serviced by the cache memory.

14. The device of claim 12 wherein the cache memory comprises a plurality of ways, and each portion of the plurality of portions includes at least one way of the cache memory.

15. The device of claim 12, wherein the security sensitive module includes a data processor core that is an instruction-based data processor core, and the cache memory is dedicated to the data processor core.

16. The device of claim 12, wherein the cache access module randomly accesses selected portions of the plurality of portions using a built-in self-test module that randomizes at least one of an address of a write access request, and a data of the write access request.

13. An integrated circuit die device comprising:

an execution module capable of performing security sensitive operations;

a cache memory comprising a plurality of portions;

a user programmable first storage location coupled to the cache to store an enable indicator;

a cache access module coupled to the cache memory to operate concurrently with the execution module executing a security sensitive operation to randomly access selected portions of the plurality of portions as defined by an indicator, wherein unselected portions of the plurality of portions are not able to be randomly accessed.

17. A method comprising:

identifying a first portion of a cache memory during operation of an integrated circuit;

executing a security sensitive operation at an execution unit of a processor core, wherein information related to the security sensitive operation is provided to the execution unit via the cache memory; and

randomly accessing the first portion of the cache, in response to being identified, during execution of the security sensitive operation.

18. The method of claim 17, wherein the core is a first processor core of an integrated circuit die having a plurality of cores including the first core, the cache being dedicated to the first core.

19. The method of claim 17, wherein the information related to the security sensitive operation that is provided to the execution unit includes storing at the cache memory at least one instruction of the security sensitive operation or operand data of the security sensitive operation at a location of the cache memory other than the first portion.

20. The method of claim 17, further using built-in self-test hardware to randomly access the first portion of the cache.

21. (canceled)

22. (canceled)

23. (canceled)

24. (canceled)

25. (canceled)

26. (canceled)