RANDOM TIMESLOT CONTROLLER FOR ENABLING BUILT-IN SELF TEST MODULE
First Claim
1. A method comprising:
- executing a security sensitive operation at a first portion of an integrated circuit die; and
randomly enabling and disabling a BIST (built-in self test) module of the integrated circuit die concurrently with executing the security operation to change power consumption of the integrated circuit die.
30 Assignments
0 Petitions
Accused Products
Abstract
A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.
31 Citations
20 Claims
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1. A method comprising:
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executing a security sensitive operation at a first portion of an integrated circuit die; and randomly enabling and disabling a BIST (built-in self test) module of the integrated circuit die concurrently with executing the security operation to change power consumption of the integrated circuit die. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A device comprising:
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a security sensitive module of an integrated circuit die to execute a security sensitive operation; a BIST (built-in self test) module to test at least a portion of the integrated circuit die; and a random value generator coupled to the security sensitive module and to the BIST module to randomly enable and disable the BIST module in response to the security sensitive module executing the security sensitive operation. - View Dependent Claims (14, 15, 16, 17)
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18. A method comprising:
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determining an environmental condition of an integrated circuit die; and randomly enabling and disabling a BIST (built-in self test) module based upon a value of the environmental condition. - View Dependent Claims (19, 20)
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Specification