INSTRUCTION THAT SPECIFIES AN APPLICATION THREAD PERFORMANCE STATE

• US 20140053009A1
• Filed: 12/22/2011
• Published: 02/20/2014
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Semin, Andrey
• Granted Patent: US 9,310,875 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus is described that includes a processor. The processor has a processing core to execute an instruction that specifies a performance state of an application thread. The instruction belongs to the application thread. The processor includes a register to store the performance state. The processor includes power management control logic coupled to the register to set a performance state of the processing core as a function of the performance state.

Claims

1. An apparatus, comprising:

a processor having;

a) a processing core to execute an instruction that specifies a performance state of an application thread, said instruction belonging to said application thread;

b) a register to store said performance state;

c) power management control logic coupled to said register to set a performance state of said processing core as a function of said performance state.

2. The apparatus of claim 1 further comprising a second register to store a system edict value that indicates whether said processor is biased toward higher performance and higher power consumption or lower performance and lower power consumption.

3. The apparatus of claim 2 wherein said power management control logic is further coupled to said second register and set said performance state of said processing core as a function of said performance state of said application thread and said system edict value.

4. The apparatus of claim 3 wherein said processor supports multiple performance states, and, said performance state of said processing core, if said system edict value indicates a bias toward higher performance and power consumption, is a next performance state higher than if said system edict value indicated a bias toward lower performance and lower power consumption.

8. The apparatus of claim 1 wherein said performance state of said processing core is a performance state of a pipeline within said processing core, said instruction executed by said pipeline.

5. The apparatus of clam 4 wherein said processor is deemed to be a shared logic block that supports multiple application threads and corresponding performance states thereof.

6. The apparatus of claim 5 wherein said performance state of said processor is a function of said performance state of said application thread because said performance state of said thread is a highest performance state amongst said multiple application threads, and, said system edict value indicates a bias toward higher performance and higher power consumption.

7. The apparatus of claim 5 wherein said performance state of said processor is a function of said performance state of said application thread because said performance state of said thread is a lowest performance state amongst said multiple application threads, and, said system edict value indicates a bias toward lower performance and lower power consumption.

9. A method, comprising:

executing on a processing core an instruction that specifies a performance state of a thread of an application, said instruction belonging to said thread, said instruction called out by said application;

changing a performance state of said processing core consistent with said performance state.

10. The method of claim 9 wherein said instruction is executed by a pipeline and said performance state of said processing core is a performance state of said pipeline.

11. The method of claim 9 further comprising:

writing said performance state of said thread to register space;

power control logic circuitry accessing said performance state of said thread from said register space and determining said changing;

12. The method of claim 10 further comprising said power control logic circuitry taking into account of a system edict value when performing said determining, said system edict value indicating whether said processing core'"'"'s processor is biased toward higher performance and higher power consumption or lower performance and lower power consumption.

13. The method of claim 12 further comprising said power control logic circuitry taking into account respective performance states of other application threads executed by said processor when performing said changing.

14. The method of claim 9 further comprising taking account of said performance state of said thread and respective performance states of other threads when determining a performance state of a logic block other than said processing core that supports said thread and said other threads, said logic block and said processing core part of a same processor semiconductor chip.

15. The method of claim 14 wherein said logic block is any of:

an L2 cache;

a system memory controller;

an I/0 hub;

an integrated special purpose computational block, such as graphics processor unit.

16. A machine readable medium containing program code that when processed by a processor causes a method to be performed, said method comprising:

executing a control thread and a plurality of worker threads, said executing including executing a first instruction for said control thread that specifies that hardware that executes said control thread is to be in a high performance state, and, executing respective instructions for each of said worker threads that each specify that respective hardware that executes said worker threads is to be placed in a lower performance state; and

,

in response to a work item being imminently presented to said worker threads, executing respective instructions for each of said worker threads that each specify that respective hardware that executes said worker threads is to be placed in a higher performance state than said lower performance state.

17. The machine readable medium of claim 16 wherein said high performance state and said higher performance state are the same performance state.

18. The machine readable medium of claim 16 wherein said higher performance state is lower than said high performance state.

19. The machine readable medium of claim 16 wherein said control thread is kept in said high performance state.

20. The machine readable medium of claim 19 wherein said control thread processes projects for said worker threads received from a network.